LMK04616 Ultra Low-Noise and Low Power JESD204B Compliant Clock Jitter Cleaner | TI.com

LMK04616 (ACTIVE)

Ultra Low-Noise and Low Power JESD204B Compliant Clock Jitter Cleaner

Ultra Low-Noise and Low Power JESD204B Compliant Clock Jitter Cleaner - LMK04616
 

Description

The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support. The 16 clock outputs can be configured to drive eight JESD204B converters or other logic devices using device and SYSREF clocks. The 17th output can be configured to provide a signal from PLL2 or a copy from the external VCXO.

Features like fully integrated PLL1 and PLL2 loop filters, a high number of integrated LDOs, digital and analog delay, the flexibility to supply outputs with 3.3V, 2.5V and 1.8V as well as the option to generate multiple SYSREF domains simultaneously makes the device easy to use.

Not limited to JESD204B applications each of the 17 outputs can be configured for traditional clocking systems.

Features

  • Dual Loop PLL Architecture
    • 65-fs RMS Jitter (10 kHz to 20 MHz)
    • 85-fs RMS Jitter (100 Hz to 20 MHz)
    • –165-dBc/Hz Noise Floor at 122.88 MHz
  • JESD204B Support
    • Single Shot, Pulsed, and Continuous SYSREF
  • 16 Differential Output Clocks in 8 Frequency Groups
    • Programmable Output Swing Between 700 mVpp to 1600 mVpp
    • Each Output Pair Can be Configured to SYSREF Clock Output
    • 16-Bit Channel Divider
    • Minimum SYSREF Frequency of 25 kHz
    • Maximum Output Frequency of 2 GHz
    • Precision Digital Delay, Dynamically Adjustable
      • Digital Delay (DDLY) of ½ × Clock Distribution Path Frequency (2 GHz Maximum)
    • 60-ps Step Analog Delay
    • 50% Duty Cycle Output Divides, 1 to 65535
      (Even and Odd)
  • 4 Reference Inputs
    • Holdover Mode, When Inputs are Lost
    • Automatic and Manual Switch-Over Modes
    • Loss-of-Signal (LOS) Detection
  • 1.05-W Typical Power Consumption With 16 Outputs Active
  • Operates Typically From a 1.8-V (Outputs, Inputs) and 3.3-V Supply (Digital, PLL1, PLL2_OSC, PLL2 Core)
  • Fully Integrated Programmable Loop Filter
  • PLL2
    • PLL2 Phase Detector Rate Up to 250 MHz
    • OSCin Frequency-Doubler
    • Integrated Low-Noise VCO
  • Internal Power Conditioning: Better Than –80dBc PSRR on VDDO for 122.88-MHz Differential Outputs
  • 3- or 4-Wire SPI Interface (4-Wire is Default)
  • –40ºC to +85ºC Industrial Ambient Temperature
  • Supports 105ºC PCB Temperature (Measured at Thermal Pad)
  • LMK04616: 10-mm × 10-mm NFBGA-144 Package With 0.8-mm Pitch

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Parametrics Compare all products in Dual / Cascaded PLL

 
Number of Outputs
Output Level
Output Frequency (Min) (MHz)
Output Frequency (Max) (MHz)
Number of Inputs
Input Level
RMS Jitter
VCO Frequency (Min) (MHz)
VCO Frequency (Max) (MHz)
Supply Voltage (Min) (V)
Supply Voltage (Max) (V)
Features
Operating Temperature Range (C)
Pin/Package
LMK04616 LMK04208 LMK04610 LMK04808 LMK04821 LMK04826 LMK04828 LMK04832
16     7     10     14     15     15     15     14    
HCSL
HSDS
LVDS
LVPECL    
LVCMOS
LVDS
LVPECL    
HCSL
HSDS
LVDS
LVPECL    
LVCMOS
LVDS
LVPECL    
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
0.03     0.329     0.03     0.22     0.045     0.225     0.289     0.305    
2000     3072     2000     3072     2075     2505     3080     3250    
4     2     2     2     3     3     3     3    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
 
0.065     0.111     0.065     0.111     0.091     0.089     0.088     0.047    
5800     2750     5800     2750     365     1840     2370     2495    
6200     3072     6200     3072     2075     2505     3080     3205    
1.7     3.15     1.7     3.15     3.15     3.15     3.15     3.15    
3.465     3.45     3.465     3.45     3.45     3.45     3.45     3.45    
105C PCB temp
Holdover mode
JESD204B SYSREF
JESD204B SYSREF Generation
Jitter Cleaner/Clock Generator/Clock Distribution
Integrated LDOs
Integrated Loop Filters
Low Power Design
Manual and automatic switching between inputs
Semi-Digital PLL
SPI    
Holdover mode
Int. xtal oscillator
Manual/auto switch
SPI
uWire    
105C PCB temp
Holdover mode
JESD204B SYSREF
JESD204B SYSREF Generation
Jitter Cleaner/Clock Generator/Clock Distribution
Integrated LDOs
Integrated Loop Filters
Low Power Design
Manual and automatic switching between inputs
Semi-Digital PLL
SPI    
uWire
SPI
Holdover mode
Manual/auto switch
Int. xtal oscillator    
105C PCB temp
Holdover mode
Int. xtal oscillator
JESD204B SYSREF Generation
Manual/auto switch
SPI
uWire    
105C PCB temp
Holdover mode
Int. xtal oscillator
JESD204B SYSREF Generation
Manual/auto switch
SPI
uWire    
105C PCB temp
Holdover mode
Int. xtal oscillator
JESD204B SYSREF Generation
Manual/auto switch
SPI
uWire    
Holdover mode
JESD204B SYSREF Generation
Manual/auto switch
SPI    
-40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85    
144NFBGA     64WQFN     56QFN     64WQFN     64WQFN     64WQFN     64WQFN     64WQFN    

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