LMK04826 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner | TI.com

LMK04826
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Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner

 

Description

The LMK0482x family is the industry’s highest performance clock conditioner with JEDEC JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high performance outputs for traditional clocking systems.

The high performance combined with features like the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay make the LMK0482x family ideal for providing flexible high performance clocking trees.

Features

  • JEDEC JESD204B Support
  • Ultra-Low RMS Jitter
    • 88 fs RMS Jitter (12 kHz to 20 MHz)
    • 91 fs RMS Jitter (100 Hz to 20 MHz)
    • –162.5 dBc/Hz Noise Floor at 245.76 MHz
  • Up to 14 Differential Device Clocks from PLL2
    • Up to 7 SYSREF Clocks
    • Maximum Clock Output Frequency 3.1 GHz
    • LVPECL, LVDS, HSDS, LCPECL
      Programmable Outputs from PLL2
  • Up to 1 Buffered VCXO/Crystal Output from PLL1
    • LVPECL, LVDS, 2xLVCMOS Programmable
  • Dual Loop PLLatinum™ PLL Architecture
  • PLL1
    • Up to 3 Redundant Input Clocks
      • Automatic and Manual Switch-Over Modes
      • Hitless Switching and LOS
    • Integrated Low-Noise Crystal Oscillator Circuit
    • Holdover mode when Input Clocks are Lost
  • PLL2
    • Normalized [1 Hz] PLL Noise Floor of
      –227 dBc/Hz
    • Phase Detector Rate up to 155 MHz
    • OSCin Frequency-Doubler
    • Two Integrated Low-Noise VCOs
  • 50% Duty Cycle Output Divides, 1 to 32
    (even and odd)
  • Precision Digital Delay, Dynamically Adjustable
  • 25 ps Step Analog Delay
  • Multi-mode: Dual PLL, single PLL, and Clock
    Distribution
  • Industrial Temperature Range: –40 to 85°C
  • Supports 105°C PCB Temperature (Measured at Thermal Pad)
  • 3.15-V to 3.45-V Operation
  • Package: 64-pin QFN (9.0 × 9.0 × 0.8 mm)

Design with LMK04826

Recommend Input Frequency Output Frequencies
 MHz
Input Frequency  MHz
 MHz  MHz

Parametrics

Compare all products in Clock jitter cleaners & synchronizers Email Download to Excel
Part number Order Function Number of outputs Output frequency (Min) (MHz) Output frequency (Max) (MHz) Supply voltage (Min) (V) RMS jitter Supply voltage (Max) (V) Input type Output type Features Rating Operating temperature range (C) Package Group Package size: mm2:W x L (PKG) Number of Inputs
LMK04826 Order now Dual-loop PLL     15     0.225     2505     3.15     0.089     3.45     LVCMOS
LVDS
LVPECL    
LVCMOS
LVDS
LVPECL    
JESD204B     Catalog     -40 to 85     WQFN | 64     64WQFN: 81 mm2: 9 x 9 (WQFN | 64)     3    
LMK04228 Order now Dual-loop PLL     15     0.315     1250     3.15     0.156     3.45       LVCMOS
LVDS
LVPECL    
JESD204B     Catalog     -40 to 85     WQFN | 64     64WQFN: 81 mm2: 9 x 9 (WQFN | 64)     3    
LMK04616 Order now Single-loop PLL     16     0.03     2000     1.7     0.065     3.465     LVCMOS
LVDS
LVPECL    
LVDS
LVPECL    
  Catalog     -40 to 85     NFBGA | 144     144NFBGA: 100 mm2: 10 x 10 (NFBGA | 144)     4    
LMK04808 Order now Dual-loop PLL     14     0.22     3072     3.15     0.111     3.45     LVCMOS
LVDS
LVPECL    
LVCMOS
LVDS
LVPECL    
0 Delay     Catalog     -40 to 85     WQFN | 64     64WQFN: 81 mm2: 9 x 9 (WQFN | 64)     2    
LMK04821 Order now Dual-loop PLL     15     0.045     2075     3.15     0.091     3.45       LVCMOS
LVDS
LVPECL    
JESD204B     Catalog     -40 to 85     WQFN | 64     64WQFN: 81 mm2: 9 x 9 (WQFN | 64)     3    
LMK04828 Order now Dual-loop PLL     15     0.289     3080     3.15     0.088     3.45     LVCMOS
LVDS
LVPECL    
LVCMOS
LVDS
LVPECL    
JESD204B     Catalog     -40 to 85     WQFN | 64     64WQFN: 81 mm2: 9 x 9 (WQFN | 64)     3    
LMK04832 Order now Dual-loop PLL     14     0.305