LMK04828

ACTIVE

Ultra-low jitter synthesizer & jitter cleaner

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Type Title Date
* Datasheet LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs datasheet (Rev. AR) Dec. 08, 2015
Application notes Multi-Clock Synchronization Dec. 30, 2019
Technical articles Solving synchronization challenges in Industrial Ethernet Jul. 19, 2019
Technical articles Step-by-step considerations for designing wide-bandwidth multichannel systems Jun. 04, 2019
User guides LMK04826/28 User’s Guide (Rev. B) Mar. 13, 2018
Technical articles Preparing for 5G applications: sync your multichannel JESD204B data acquisition systems up to 15 GHz Aug. 28, 2017
Technical articles High speed data converter clocking for JESD204B Jul. 07, 2017
Selection guides TI Components for Aerospace and Defense Guide (Rev. E) Mar. 22, 2017
Selection guides Clock & Timing Solutions (Rev. C) Jan. 19, 2017
Application notes RF Sampling ADC with 800MHz of IBW LTE Sep. 08, 2016
User guides TSW12J54EVM User's Guide Oct. 21, 2015
User guides TSW54J60 Evaluation Module User's Guide (Rev. A) Sep. 21, 2015
Application notes Analog Applications Journal 2Q 2015 Apr. 28, 2015
Application notes JESD204B multi-device synchronization: Breaking down the requirements Apr. 28, 2015
Selection guides Analog for Xilinx (R) FPGAs Selection Guide - 2015 (Rev. B) Jan. 07, 2015
Application notes When is the JESD204B interface the right choice? Jan. 22, 2014
User guides HSDC-SEK-10 Jan. 17, 2013
Application notes LMK04828 as a Clock Source for the ADS42JB69 Nov. 14, 2012