SNAS517E November   2011  – September 2015 LMP91050

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Interface
    7. 7.7 Timing Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Programmable Gain Amplifier
      2. 8.3.2 External Filter
      3. 8.3.3 Offset Adjust
      4. 8.3.4 Common-Mode Generation
      5. 8.3.5 CSB
        1. 8.3.5.1 SCLK
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 SPI Interface
        1. 8.5.1.1 Interface Pins
        2. 8.5.1.2 Communication Protocol
        3. 8.5.1.3 Registers Organization
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration
      2. 8.6.2 DAC Configuration
      3. 8.6.3 SDIO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Programmable Gain Amplifier
  • Dark Signal Offset Cancellation
  • Supports External Filtering
  • Common-Mode Generator and 8-Bit DAC
  • Key Specifications
    • Programmable Gain 167 to 7986 V/V
    • Low Noise (0.1 to 10 Hz) 0.1 μVRMS
    • Gain Drift 100 ppm/°C (Maximum)
    • Phase Delay Drift 500 ns (Maximum)
    • Power Supply Voltage Range 2.7 to 5.5 V

2 Applications

  • NDIR Sensing
  • Demand Control Ventilation
  • Building Monitoring
  • CO2 Cabin Control — Automotive
  • Alcohol Detection — Automotive
  • Industrial Safety and Security
  • GHG and Freons Detection Platforms

3 Description

The LMP91050 device is a programmable integrated Sensor Analog Front End (AFE) optimized for thermopile sensors, as typically used in NDIR applications. It provides a complete signal path solution between a sensor and microcontroller that generates an output voltage proportional to the thermopile voltage. The programmability of the LMP91050 enables it to support multiple thermopile sensors with a single design as opposed to the multiple discrete solutions.

The LMP91050 features a programmable gain amplifier (PGA), dark phase offset cancellation, and an adjustable common-mode generator (1.15 V or 2.59 V) which increases output dynamic range. The PGA offers a low-gain range of 167 V/V to 1335 V/V plus a high-gain range of 1002 V/V to 7986 V/V which enables the user to use thermopiles with different sensitivities. The PGA is highlighted by low-gain drift (100 ppm/°C), output offset drift (1.2 mV/°C at G = 1002 V/V), phase delay drift (500 ns) and noise specifications (0.1 μVRMS 0.1 to 10Hz).

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LMP91050 VSSOP (10) 3.00 mm × 3.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Circuit

LMP91050 30164111.gif
Configurable AFE for NDIR