SNOS998I February 2002  – October 2015 LMV761 , LMV762 , LMV762Q-Q1

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: LMV761, LMV762
    3. 6.3 ESD Ratings: LMV762Q-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6  2.7-V Electrical Characteristics
    7. 6.7  5-V Electrical Characteristics
    8. 6.8 2-V Switching Characteristics
    9. 6.9 5-V Switching Characteristics
    10. 6.10Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1Basic Comparator
      2. 7.3.2Hysteresis
      3. 7.3.3Input
    4. 7.4Device Functional Modes
      1. 7.4.1Shutdown Mode
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
      2. 8.2.2Detailed Design Procedure
      3. 8.2.3Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Documentation Support
      1. 11.1.1Related Links
    2. 11.2Community Resources
    3. 11.3Trademarks
    4. 11.4Electrostatic Discharge Caution
    5. 11.5Glossary
  12. 12Mechanical, Packaging, and Orderable Information

9 Power Supply Recommendations

To minimize supply noise, power supplies must be decoupled by a 0.1-μF ceramic capacitor in parallel with a
10-μF capacitor.

Due to the nanosecond edges on the output transition, peak supply currents will be drawn during output transitions. Peak current depends on the capacitive loading on the output. The output transition can cause transients on poorly bypassed power supplies. These transients can cause a poorly bypassed power supply to ring due to trace inductance and low self-resonance frequency of high ESR bypass capacitors.

Treat the LMV6x as a high-speed device. Keep the ground paths short and place small (low-ESR ceramic) bypass capacitors directly between the V+ and V pins.

Output capacitive loading and output toggle rate will cause the average supply current to rise over the quiescent current.