SNAS654A March 2015  – July 2016 LMX2571

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6Timing Requirements
    7. 6.7Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1 Reference Oscillator Input
      2. 7.3.2 R-Dividers and Multiplier
      3. 7.3.3 PLL Phase Detector and Charge Pump
      4. 7.3.4 PLL N-Divider and Fractional Circuitry
      5. 7.3.5 Partially Integrated Loop Filter
      6. 7.3.6 Low-Noise, Fully Integrated VCO
      7. 7.3.7 External VCO Support
      8. 7.3.8 Programmable RF Output Divider
      9. 7.3.9 Programmable RF Output Buffer
      10. 7.3.10Integrated TX, RX Switch
      11. 7.3.11Powerdown
      12. 7.3.12Lock Detect
      13. 7.3.13FSK Modulation
      14. 7.3.14FastLock
      15. 7.3.15Register Readback
    4. 7.4Device Functional Modes
      1. 7.4.1Operation Mode
      2. 7.4.2Duplex Mode
      3. 7.4.3FSK Mode
    5. 7.5Programming
      1. 7.5.1Recommended Initial Power on Programming Sequence
      2. 7.5.2Recommended Sequence for Changing Frequencies
    6. 7.6Register Maps
      1. 7.6.1 R60 Register (offset = 3Ch) [reset = 4000h]
      2. 7.6.2 R58 Register (offset = 3Ah) [reset = C00h]
      3. 7.6.3 R53 Register (offset = 35h) [reset = 2802h]
      4. 7.6.4 R47 Register (offset = 2Fh) [reset = 0h]
      5. 7.6.5 R46 Register (offset = 2Eh) [reset = 1Ah]
      6. 7.6.6 R42 Register (offset = 2Ah) [reset = 210h]
      7. 7.6.7 R41 Register (offset = 29h) [reset = 810h]
      8. 7.6.8 R40 Register (offset = 28h) [reset = 101Ch]
      9. 7.6.9 R39 Register (offset = 27h) [reset = 11F0h]
      10. 7.6.10R35 Register (offset = 23h) [reset = 647h]
      11. 7.6.11R34 Register (offset = 22h) [reset = 1000h]
      12. 7.6.12R33 Register (offset = 21h) [reset = 0h]
      13. 7.6.13R25 to R32 Register (offset = 19h to 20h) [reset = 0h]
      14. 7.6.14R24 Register (offset = 18h) [reset = 10h]
      15. 7.6.15R23 Register (offset = 17h) [reset = 10A4h]
      16. 7.6.16R22 Register (offset = 16h) [reset = 8584h]
      17. 7.6.17R21 Register (offset = 15h) [reset = 101h]
      18. 7.6.18R20 Register (offset = 14h) [reset = 28h]
      19. 7.6.19R19 Register (offset = 13h) [reset = 0h]
      20. 7.6.20R18 Register (offset = 12h) [reset = 0h]
      21. 7.6.21R17 Register (offset = 11h) [reset = 0h]
      22. 7.6.22R9 to R16 Register (offset = 9h to 10h) [reset = 0h]
      23. 7.6.23R8 Register (offset = 8h) [reset = 10h]
      24. 7.6.24R7 Register (offset = 7h) [reset = 10A4h]
      25. 7.6.25R6 Register (offset = 6h) [reset = 8584h]
      26. 7.6.26R5 Register (offset = 5h) [reset = 101h]
      27. 7.6.27R4 Register (offset = 4h) [reset = 28h]
      28. 7.6.28R3 Register (offset = 3h) [reset = 0h]
      29. 7.6.29R2 Register (offset = 2h) [reset = 0h]
      30. 7.6.30R1 Register (offset = 1h) [reset = 0h]
      31. 7.6.31R0 Register (offset = 0h) [reset = 3h]
  8. Application and Implementation
    1. 8.1Application Information
      1. 8.1.1 Direct Digital FSK Modulation
      2. 8.1.2 Frequency and Output Port Switching with TrCtl Pin
      3. 8.1.3 OSCin Configuration
      4. 8.1.4 Register R0 F1F2_INIT, F1F2_MODE usage
      5. 8.1.5 FastLock with External VCO
      6. 8.1.6 OSCin Slew Rate
      7. 8.1.7 RF Output Buffer Power Control
      8. 8.1.8 RF Output Buffer Type
      9. 8.1.9 MULT Multiplier
      10. 8.1.10Integrated VCO
    2. 8.2Typical Applications
      1. 8.2.1Synthesizer Duplex Mode
        1. 8.2.1.1Design Requirements
        2. 8.2.1.2Detailed Design Procedure
        3. 8.2.1.3Synthesizer Duplex Mode Application Curves
      2. 8.2.2PLL Duplex Mode
        1. 8.2.2.1Design Requirements
        2. 8.2.2.2Detailed Design Procedure
        3. 8.2.2.3PLL Duplex Mode Application Curves
      3. 8.2.3Synthesizer/PLL Duplex Mode
        1. 8.2.3.1Design Requirements
        2. 8.2.3.2Detailed Design Procedure
        3. 8.2.3.3Synthesizer/PLL Duplex Mode Application Curves
    3. 8.3Do's and Don'ts
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Device Support
      1. 11.1.1Development Support
    2. 11.2Documentation Support
      1. 11.2.1Related Documentation
    3. 11.3Trademarks
    4. 11.4Electrostatic Discharge Caution
    5. 11.5Glossary
  12. 12Mechanical, Packaging, and Orderable Information

1 Features

  • Any Frequency from 10 MHz to 1344 MHz
  • Low Phase Noise and Spurs
    • –123 dBc/Hz at 12.5 kHz Offset at 480 MHz
    • –145 dBc/Hz at 1 MHz Offset at 480 MHz
    • Normalized PLL Noise Floor of –231 dBc/Hz
    • Spurious Better Than –75 dBc/Hz
  • New FastLock to Reduce Lock Time
  • A Novel Technique to Remove Integer Boundary Spurs
  • Integrated 5-V Charge Pump and Output Divider for External VCO Operation
  • 2-, 4- and 8-Level or Arbitrary Level Direct Digital FSK Modulation
  • One TX/RX Output or Two Fanout Outputs
  • Crystal, XO or Differential Reference Clock Input
  • Low Current Consumption
    • 39-mA Typical Synthesizer Mode (Internal VCO)
    • 9-mA Typical PLL Mode (External VCO)
  • 24-Bit Fractional-N Delta Sigma Modulator

2 Applications

  • Duplex Mode Digital Professional 2-Way Radio
    • dPMR, DMR, PDT, P25 Phase I
  • Low Power Radio Communication Systems
    • Satcom Modem
    • Wireless Microphone
    • Propriety Wireless Connectivity
  • Handheld Test and Measurement Equipment

3 Description

The LMX2571 is a low-power, high-performance, wideband PLLatinum™ RF synthesizer that integrates a delta-sigma fractional N PLL, multiple core voltage-controlled oscillator (VCO), programmable output dividers and two output buffers. The VCO cores work up to 5.376 GHz resulting in continuous output frequency range of 10 MHz to 1344 MHz.

This synthesizer can also be used with an external VCO. To that end, a dedicated 5-V charge pump and an output divider are available for this configuration.

A unique programmable multiplier is also incorporated to help improve spurs, allowing the system to use every channel even if it falls on an integer boundary.

The output has an integrated SPDT switch that can be used as a transmit/receive switch in FDD radio application. Both outputs can also be turned on to provide 2 outputs at the same time.

The LMX2571 supports direct digital FSK modulation through programming or pins. Discrete level FSK, pulse shaping FSK, and analog FM modulation are supported.

A new FastLock technique can be used allowing the user to step from one frequency to the next in less than 1.5 ms even when an external VCO is used with a narrow band loop filter.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
LMX2571WQFN (36)6.00 mm × 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

LMX2571 4_SimSch_SNAS654.gif