SNAS680D December 2015  – November 2017 LMX2582


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6Timing Requirements
    7. 6.7Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Functional Description
      1. 7.3.1 Input Signal
      2. 7.3.2 Input Signal Path
      3. 7.3.3 PLL Phase Detector and Charge Pump
      4. 7.3.4 N Divider and Fractional Circuitry
      5. 7.3.5 Voltage Controlled Oscillator
      6. 7.3.6 VCO Calibration
      7. 7.3.7 Channel Divider
      8. 7.3.8 Output Distribution
      9. 7.3.9 Output Buffer
      10. 7.3.10Phase Adjust
    4. 7.4Device Functional Modes
      1. 7.4.1Power Down
      2. 7.4.2Lock Detect
      3. 7.4.3Register Readback
    5. 7.5Programming
      1. 7.5.1Recommended Initial Power on Programming Sequence
      2. 7.5.2Recommended Sequence for Changing Frequencies
    6. 7.6Register Maps
      1. 7.6.1LMX2582 Register Map - Default Values
        1. Descriptions
  8. Application and Implementation
    1. 8.1Application Information
      1. 8.1.1Optimization of Spurs
        1. Spurs by Offsets
        2. Mitigation Techniques
      2. 8.1.2Configuring the Input Signal Path
        1. Signal Noise Scaling
      3. 8.1.3Input Pin Configuration
      4. 8.1.4Using the OSCin Doubler
      5. 8.1.5Using the Input Signal Path Components
        1. Phase Detector Frequency
        2. and Dividing by the Same Value
      6. 8.1.6Designing for Output Power
      7. 8.1.7Current Consumption Management
      8. 8.1.8Decreasing Lock Time
      9. 8.1.9Modeling and Understanding PLL FOM and Flicker Noise
    2. 8.2Typical Application
      1. 8.2.1Design for Low Jitter
        1. Requirements
        2. Design Procedure
        3. Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Device Support
      1. 11.1.1Development Support
    2. 11.2Documentation Support
      1. 11.2.1Related Documentation
    3. 11.3Receiving Notification of Documentation Updates
    4. 11.4Community Resources
    5. 11.5Trademarks
    6. 11.6Electrostatic Discharge Caution
    7. 11.7Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHA|40
Orderable Information


  • Output Frequency Range from 20 to 5500 MHz
  • Industry Leading Phase Noise Performance
    • VCO Phase Noise: –144.5 dBc/Hz at 1-MHz Offset for 1.8-GHz Output
    • Normalized PLL Noise Floor: –231 dBc/Hz
    • Normalized PLL Flicker Noise: –126 dBc/Hz
    • 47-fs RMS Jitter (12 kHz to 20 MHz) for 1.8 GHz Output
  • Input Clock Frequency Up to 1400 MHz
  • Phase Detector Frequency Up to 200 MHz,
    and Up to 400 MHz in Integer-N Mode
  • Supports Fractional-N and Integer-N Modes
  • Dual Differential Outputs
  • Innovative Solution to Reduce Spurs
  • Programmable Phase Adjustment
  • Programmable Charge Pump Current
  • Programmable Output Power Level
  • SPI or uWire (4-Wire Serial Interface)
  • Single Power Supply Operation: 3.3 V


  • Test and Measurement Equipment
  • Cellular Base-Station
  • Microwave Backhaul
  • High-Performance Clock Source for High-Speed Data Converters
  • Software Defined Radio


The LMX2582 device is a low-noise, wideband RF PLL with integrated VCO that supports a frequency range from 20 MHz to 5.5 GHz. The device supports both fractional-N and integer-N modes, with a 32-bit fractional divider allowing fine frequency selection. Integrated noise of 47 fs for 1.8-GHz output makes it an ideal low-noise source. Combining best-in-class PLL and integrated VCO noise with integrated LDOs, this device removes the need for multiple discrete devices in high performance systems.

The device accepts input frequencies up to 1.4 GHz, which combined with frequency dividers and programmable low noise multiplier allows flexible frequency planning. The additional programmable low-noise multiplier lets users mitigate the impact of integer boundary spurs. In Fractional-N mode, the device can adjust the output phase by a 32-bit resolution. For applications that need fast frequency changes, the device supports a fast calibration option which takes less than 25 µs.

This performance is achieved by using single 3.3-V supply. It supports 2 flexible differential outputs that can be configured as single-ended outputs as well. Users can choose to program one output from the VCO and the second from the channel divider. When not being used, each output can be muted separately.

Device Information (1)


WQFN (40) 6.00 mm × 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.
  2. T = Tape; R = Reel

Simplified Schematic

LMX2582 LMX2582_block_diagram_snas680.gif