SNAS736A June 2017  – August 2017 LMX2595

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6Timing Requirements
    7. 6.7Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1 Reference Oscillator Input
      2. 7.3.2 Reference Path
        1. 7.3.2.1OSCin Doubler (OSC_2X)
        2. 7.3.2.2Pre-R Divider (PLL_R_PRE)
        3. 7.3.2.3Programmable Multiplier (MULT)
        4. 7.3.2.4Post-R Divider (PLL_R)
      3. 7.3.3 PLL Phase Detector and Charge Pump
      4. 7.3.4 N Divider and Fractional Circuitry
      5. 7.3.5 MUXout Pin
        1. 7.3.5.1Lock Detect
        2. 7.3.5.2Readback
      6. 7.3.6 VCO (Voltage Controlled Oscillator)
        1. 7.3.6.1VCO Calibration
        2. 7.3.6.2Determining the VCO Gain
      7. 7.3.7 Channel Divider
      8. 7.3.8 VCO Doubler
      9. 7.3.9 Output Buffer
      10. 7.3.10Powerdown Modes
      11. 7.3.11Phase Synchronization
        1. 7.3.11.1General Concept
        2. 7.3.11.2Categories of Applications for SYNC
        3. 7.3.11.3Procedure for Using SYNC
        4. 7.3.11.4SYNC Input Pin
      12. 7.3.12Phase Adjust
      13. 7.3.13Fine Adjustments for Phase Adjust and Phase SYNC
      14. 7.3.14Ramping Function
        1. 7.3.14.1Manual Pin Ramping
          1. 7.3.14.1.1Manual Pin Ramping Example
        2. 7.3.14.2Automatic Ramping
          1. 7.3.14.2.1Automatic Ramping Example (Triangle Wave)
      15. 7.3.15SYSREF
        1. 7.3.15.1Programmable Fields
        2. 7.3.15.2Input and Output Pin Formats
          1. 7.3.15.2.1Input Format for SYNC and SYSREF Pins
          2. 7.3.15.2.2SYSREF Output Format
        3. 7.3.15.3Examples
        4. 7.3.15.4SYSREF Procedure
      16. 7.3.16SysRefReq Pin
    4. 7.4Device Functional Modes
    5. 7.5Programming
      1. 7.5.1Recommended Initial Power-Up Sequence
      2. 7.5.2Recommended Sequence for Changing Frequencies
    6. 7.6Register Maps and Descriptions
      1. 7.6.1 General Registers R0, R1, & R7
      2. 7.6.2 Input Path Registers
      3. 7.6.3 Charge Pump Registers (R13, R14)
      4. 7.6.4 VCO Calibration Registers
      5. 7.6.5 N Divider, MASH, and Output Registers
      6. 7.6.6 SYNC and SysRefReq Input Pin Register
      7. 7.6.7 Lock Detect Registers
      8. 7.6.8 MASH_RESET
      9. 7.6.9 SysREF Registers
      10. 7.6.10CHANNEL Divider Registers
      11. 7.6.11Ramping and Calibration Fields
      12. 7.6.12Ramping Registers
        1. 7.6.12.1Ramp Limits
        2. 7.6.12.2Ramping Triggers, Burst Mode, and RAMP0_RST
        3. 7.6.12.3Ramping Configuration
      13. 7.6.13Readback Registers
  8. Application and Implementation
    1. 8.1Application Information
      1. 8.1.1OSCin Configuration
      2. 8.1.2OSCin Slew Rate
      3. 8.1.3RF Output Buffer Power Control
      4. 8.1.4RF Output Buffer Pullup
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
      2. 8.2.2Detailed Design Procedure
      3. 8.2.3Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Device Support
      1. 11.1.1Third-Party Products Disclaimer
      2. 11.1.2Development Support
    2. 11.2Documentation Support
      1. 11.2.1Related Documentation
    3. 11.3Receiving Notification of Documentation Updates
    4. 11.4Community Resources
    5. 11.5Trademarks
    6. 11.6Electrostatic Discharge Caution
    7. 11.7Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

Features

  • 10-MHz to 19-GHz Output Frequency
  • –110 dBc/Hz Phase Noise at 100-kHz Offset With 15-GHz Carrier
  • 45-fs rms Jitter at 7.5 GHz (100 Hz to 100 MHz)
  • Programmable Output Power
  • PLL Key Specifications
    • Figure of Merit: –236 dBc/Hz
    • Normalized 1/f Noise: –129 dBc/Hz
    • High Phase Detector Frequency
      • 400-MHz Integer Mode
      • 300-MHz Fractional Mode
    • 32-bit Fractional-N Divider
  • Remove Integer Boundary Spurs With Programmable Input Multiplier
  • Synchronization of Output Phase Across Multiple Devices
  • Support for SYSREF With 9-ps Resolution Programmable Delay
  • Frequency Ramp and Chirp Generation Ability for FMCW Applications
  • < 20-µs VCO Calibration Speed
  • 3.3-V Single Power Supply Operation

Applications

  • 5G and mm-Wave Wireless Infrastructure
  • Test and Measurement Equipment
  • Radar
  • MIMO
  • Phased Array Antennas and Beam Forming
  • High-Speed Data Converter Clocking (Supports JESD204B)

Description

The LMX2595 high-performance, wideband synthesizer that can generate any frequency from 10 MHz to 19 GHz. An integrated doubler is used for frequencies above 15 GHz.   The high performance PLL with figure of merit of –236 dBc/Hz and high-phase detector frequency can attain very low in-band noise and integrated jitter. The high speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input  multiplier to mitigate integer boundary spurs.

The LMX2595 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. A frequency ramp generator can synthesize up to 2 segments of ramp in an automatic ramp generation option or a manual option for maximum flexibility. The fast calibration algorithm allows changing frequencies faster than 20 µs. The LMX2595 adds support for generating or repeating SYSREF (compliant to JESD204B standard) making it an ideal low-noise clock source for high-speed data converters. Fine delay adjustment (9-ps resolution) is provided in this configuration to account for delay differences of  board traces.

The output drivers within LMX2595 deliver output power as high as 7 dBm at 15-GHz carrier frequency. The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for on-board low noise LDOs.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
LMX2595VQFN (40)6.00 mm × 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

LMX2595 fbd_snas736.gif