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The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2995 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DDR DIMMS.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | LP2995 DDR Termination Regulator datasheet (Rev. M) | 19 Mar 2013 | |
| Application note | Limiting DDR Termination Regulators’ Inrush Current | 23 Aug 2016 | ||
| EVM User's guide | AN-1241 LP2995 Evaluation Board (Rev. B) | 07 May 2013 | ||
| Application note | AN-1254 DDR-SDRAM Termination Simplified Using a Linear Regulator (Rev. A) | 06 May 2013 | ||
| Application note | DDR-SDRAM Termination Simplified Using A Linear Regulator | 23 Jul 2002 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | Download |
|---|---|---|
| HSOIC (DDA) | 8 | View options |
| SOIC (D) | 8 | View options |
| WQFN (NHP) | 16 | View options |
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