SNVSAW2A April 2017  – November 2017 LP87524B-Q1 , LP87524J-Q1

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6I2C Serial Bus Timing Requirements
    7. 6.7Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Descriptions
      1. 7.3.1DC-DC Converters
        1. 7.3.1.1Overview
        2. 7.3.1.2Transition Between PWM and PFM Modes
        3. 7.3.1.3Buck Converter Load-Current Measurement
        4. 7.3.1.4Spread-Spectrum Mode
      2. 7.3.2Sync Clock Functionality
      3. 7.3.3Power-Up
      4. 7.3.4Regulator Control
        1. 7.3.4.1Enabling and Disabling Regulators
        2. 7.3.4.2Changing Output Voltage
      5. 7.3.5Enable and Disable Sequences
      6. 7.3.6Device Reset Scenarios
      7. 7.3.7Diagnosis and Protection Features
        1. 7.3.7.1Power-Good Information (PGOOD pin)
        2. 7.3.7.2Warnings for Diagnosis (Interrupt)
          1. 7.3.7.2.1Output Power Limit
          2. 7.3.7.2.2Thermal Warning
        3. 7.3.7.3Protection (Regulator Disable)
          1. 7.3.7.3.1 Short-Circuit and Overload Protection
          2. 7.3.7.3.2Overvoltage Protection
          3. 7.3.7.3.3Thermal Shutdown
        4. 7.3.7.4Fault (Power Down)
          1. 7.3.7.4.1Undervoltage Lockout
      8. 7.3.8GPIO Signal Operation
      9. 7.3.9Digital Signal Filtering
    4. 7.4Device Functional Modes
      1. 7.4.1Modes of Operation
    5. 7.5Programming
      1. 7.5.1I2C-Compatible Interface
        1. 7.5.1.1Data Validity
        2. 7.5.1.2Start and Stop Conditions
        3. 7.5.1.3Transferring Data
        4. 7.5.1.4I2C-Compatible Chip Address
        5. 7.5.1.5Auto-Increment Feature
    6. 7.6Register Maps
      1. 7.6.1Register Descriptions
        1. 7.6.1.1 OTP_REV
        2. 7.6.1.2 BUCK0_CTRL1
        3. 7.6.1.3 BUCK1_CTRL1
        4. 7.6.1.4 BUCK2_CTRL1
        5. 7.6.1.5 BUCK3_CTRL1
        6. 7.6.1.6 BUCK0_VOUT
        7. 7.6.1.7 BUCK0_FLOOR_VOUT
        8. 7.6.1.8 BUCK1_VOUT
        9. 7.6.1.9 BUCK1_FLOOR_VOUT
        10. 7.6.1.10BUCK2_VOUT
        11. 7.6.1.11BUCK2_FLOOR_VOUT
        12. 7.6.1.12BUCK3_VOUT
        13. 7.6.1.13BUCK3_FLOOR_VOUT
        14. 7.6.1.14BUCK0_DELAY
        15. 7.6.1.15BUCK1_DELAY
        16. 7.6.1.16BUCK2_DELAY
        17. 7.6.1.17BUCK3_DELAY
        18. 7.6.1.18GPIO2_DELAY
        19. 7.6.1.19GPIO3_DELAY
        20. 7.6.1.20RESET
        21. 7.6.1.21CONFIG
        22. 7.6.1.22INT_TOP1
        23. 7.6.1.23INT_TOP2
        24. 7.6.1.24INT_BUCK_0_1
        25. 7.6.1.25INT_BUCK_2_3
        26. 7.6.1.26TOP_STAT
        27. 7.6.1.27BUCK_0_1_STAT
        28. 7.6.1.28BUCK_2_3_STAT
        29. 7.6.1.29TOP_MASK1
        30. 7.6.1.30TOP_MASK2
        31. 7.6.1.31BUCK_0_1_MASK
        32. 7.6.1.32BUCK_2_3_MASK
        33. 7.6.1.33SEL_I_LOAD
        34. 7.6.1.34I_LOAD_2
        35. 7.6.1.35I_LOAD_1
        36. 7.6.1.36PGOOD_CTRL1
        37. 7.6.1.37PGOOD_CTRL2
        38. 7.6.1.38PGOOD_FLT
        39. 7.6.1.39PLL_CTRL
        40. 7.6.1.40PIN_FUNCTION
        41. 7.6.1.41GPIO_CONFIG
        42. 7.6.1.42GPIO_IN
        43. 7.6.1.43GPIO_OUT
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
        1. 8.2.1.1Inductor Selection
        2. 8.2.1.2Input Capacitor Selection
        3. 8.2.1.3Output Capacitor Selection
        4. 8.2.1.4Snubber Components
        5. 8.2.1.5Supply Filtering Components
      2. 8.2.2Detailed Design Procedure
      3. 8.2.3Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Device Support
      1. 11.1.1Third-Party Products Disclaimer
    2. 11.2Receiving Notification of Documentation Updates
    3. 11.3Community Resources
    4. 11.4Trademarks
    5. 11.5Electrostatic Discharge Caution
    6. 11.6Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNF|26
Orderable Information

Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature
  • Input Voltage: 2.8 V to 5.5 V
  • Output Voltage: 0.6 V to 3.36 V
  • Four High-Efficiency Step-Down DC-DC Converter Cores:
    • Total Output Current Up To 10 A
    • Output Voltage Slew-Rate 3.8 mV/µs
  • 4-MHz Switching Frequency
  • Spread-Spectrum Mode and Phase Interleaving
  • Configurable General Purpose I/O (GPIOs)
  • I2C-Compatible Interface which Supports Standard (100 kHz), Fast (400 kHz), Fast+ (1 MHz), and High-Speed (3.4 MHz) Modes
  • Interrupt Function with Programmable Masking
  • Programmable Power Good Signal (PGOOD)
  • Output Short-Circuit and Overload Protection
  • Overtemperature Warning and Protection
  • Overvoltage Protection (OVP) and Undervoltage Lockout (UVLO)

Applications

    Automotive Infotainment, Cluster, Radar, and Camera Power Applications

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    Simplified Schematic

    LP87524B-Q1 LP87524J-Q1 Schem_4.gif

Description

The LP87524B/J-Q1 is designed to meet the power management requirements of the latest processors and platforms in various automotive power applications. The device contains four step-down DC-DC converter cores, which are configured as 4 single phase outputs. The device is controlled by an I2C-compatible serial interface and by enable signals.

The automatic PFM/PWM (AUTO mode) operation maximizes efficiency over a wide output-current range. The LP87524B/J-Q1 supports remote voltage sensing to compensate IR drop between the regulator output and the point-of-load (POL) thus improving the accuracy of the output voltage. In addition the switching clock can be forced to PWM mode and also synchronized to an external clock to minimize the disturbances.

The LP87524B/J-Q1 device supports load-current measurement without the addition of external current-sense resistors. In addition, the LP87524B/J-Q1 supports programmable start-up and shutdown delays and sequences synchronized to enable signals. The sequences can also include GPIO signals to control external regulators, load switches and processor reset. During start-up and voltage change, the device controls the output slew rate to minimize output voltage overshoot and the in-rush current.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
LP87524B-Q1VQFN-HR (26)4.50 mm × 4.00 mm
LP87524J-Q1
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Output Voltage Options

PART NUMBERVOLTAGE
LP87524B-Q1Buck2 1.8 V, Buck3 2.3 V
LP87524J-Q1Buck2 1 V, Buck3 1.8 V

Efficiency vs Output Current

LP87524B-Q1 LP87524J-Q1 D922_LP8756.gif

Revision History

Changes from * Revision (April 2017) to A Revision

  • Added LP87524J-Q1 GPN to SNVSAW2 data sheet Go