LPV801/LPV802 320 nA Nanopower Operational Amplifiers (Rev. B)
SNOSCZ3B – August2016 – revisedNovember 2016
10.1 Layout Guidelines
The V+ pin should be bypassed to ground with a low ESR capacitor.
The optimum placement is closest to the V+ and ground pins.
Care should be taken to minimize the loop area formed by the bypass capacitor connection between V+ and ground.
The ground pin should be connected to the PCB ground plane at the pin of the device.
The feedback components should be placed as close to the device as possible to minimize strays.
10.2 Layout Example
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