SNOSD36A August   2017  – December 2017 LPV821

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Low-Side, Always-On Current Sense
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: LPV821 DBV
    2.     Pin Functions: LPV822 DSG (Preview)
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Voltage
      2. 8.3.2 Input
      3. 8.3.3 Internal Offset Correction
      4. 8.3.4 Input Offset Voltage Drift
    4. 8.4 Device Functional Modes
      1. 8.4.1 EMI Performance and Input Filtering
      2. 8.4.2 Driving Capacitive Load
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Low-Side Current Measurement
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.1.2 Detailed Design Procedure

Referring to Figure 40, the load current passing though the shunt resistor (Rshunt) develops the shunt voltage, Vshunt across the resistor. The shunt voltage is then amplified by the LPV821 by the ratio of R4 by R3 . The gain of the difference amplifier is set by the ratio of R4 to R3 . To minimize errors, set R2 = R4 and R1 = R3 . The bias voltage is supplied by buffering a resistor divider using a second LPV821 nanopower op amp. The circuit equations are provided below.

Equation 2. Vout = Vshunt * Gain Diff + Vbias
Equation 3. Vshunt = Iload * Rshunt
Equation 4. GainDiff = R4 / R3
Equation 5. Vbias = [R6 / (R6 + R5)] * VCC
Equation 6. Rshunt = [Vshunt (max)] / [Iload (max)]

Because Vshunt is a low-side measurement, a maximum value 100 mV was selected.

Equation 7. Rshunt= Vshunt/ Iload= 100mV /1A =100mΩ

The tolerance of the shunt resistor, the ratio of R4 to R3 and the ratio of R2 to R1 are the main sources of gain error in the signal path. To optimize the cost, a shut resistor with a tolerance of 0.5% was chosen. The main sources of offset errors in the circuit are the voltage divider network comprise of R5, R6 and how closely the ratio of R4 / R3 matches the ration of R2 / R1. The latter value affects the CMRR of the difference amplifier, ultimately translating to an offset error.

The shunt voltage is scaled down by a divider network made of R1 and R2 before reaching the LPV821 amplifier stage. The voltage present at the non-inverting node of the LPV821 should not exceed the common-mode range of the device. The extremely low offset voltage and drift of the LPV821 ensures minimized offset error in the measurement.

In case a bi-direction current sensing is required, for symmetric load current of –1 A to 1 A, the voltage divider resistors R5 and R6 must be equal. To minimize power consumption, 100-kΩ resistors with a tolerance of 0.5% were selected.

To set the gain of the difference amplifier, the common-mode range and output swing of the LPV821 must be considered. The gain of the difference amplifier can now be calculated as shown below

Equation 8. Gain = [Vout (max) - Vout (min)] / [Rshunt * (Imax – Imin )] = [3.2 V - 100 mV] / [100 mΩ] * [1A – ( –1A)] = 15.5 V / V