SNOSD36A August   2017  – December 2017 LPV821

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Low-Side, Always-On Current Sense
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: LPV821 DBV
    2.     Pin Functions: LPV822 DSG (Preview)
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Voltage
      2. 8.3.2 Input
      3. 8.3.3 Internal Offset Correction
      4. 8.3.4 Input Offset Voltage Drift
    4. 8.4 Device Functional Modes
      1. 8.4.1 EMI Performance and Input Filtering
      2. 8.4.2 Driving Capacitive Load
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Low-Side Current Measurement
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.2 Driving Capacitive Load

The LPV821 is internally compensated for stable unity-gain operation, with a 8-kHz typical gain bandwidth. However, the unity-gain follower is the most sensitive configuration-to-capacitive load. The combination of a capacitive load placed directly on the output of an amplifier along with the output impedance of the amplifier creates a phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the response is under-damped, which causes peaking in the transfer and, when there is too much peaking, the op amp might start oscillating.

LPV821 Cap-drive-SNOSD36.gifFigure 38. Resistive Isolation of Capacitive Load

In order to drive heavy (> 50 pF) capacitive loads, use an isolation resistor, RISO, as shown in Figure 38. The value of the RISO to be used should be decided depending on the size of the CLand the level of performance desired. Recommended minimum values for RISO are given in the following table, for 3.3V supply. Figure 39 shows the typical response obtained with the CL = 50 pF RISO = 160 kΩ. By using the isolation resistor, the capacitive load is isolated from the output of the amplifier. The larger the value of RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback loop is stable, independent of the value of CL. However, larger values of RISO (e.g. 50 kΩ) result in reduced output swing and reduced output current drive.

Table 1. Capacitive Loads vs. Needed Isolation Resistors

CLRISO
0 – 20 pF not needed
50 pF 160 kΩ
100 pF 140 kΩ
500 pF 54.9 kΩ
1 nF 33 kΩ
5 nF 15 kΩ
10 nF 5.62 kΩ
LPV821 template-with-boundry-lines.gifFigure 39. Typical Step Response