Product details

Technology family LSF Applications I2C, MDIO, SMBus Bits (#) 4 Data rate (max) (Mbps) 100 High input voltage (min) (V) 0.9 High input voltage (max) (V) 5.5 Vout (min) (V) 0.9 Vout (max) (V) 5.5 IOH (max) (mA) 0 IOL (max) (mA) 0 Supply current (max) (µA) 0.01 Features Output enable Input type Transmission Gate Output type 3-State, Transmission Gate Rating Automotive Operating temperature range (°C) -40 to 125
Technology family LSF Applications I2C, MDIO, SMBus Bits (#) 4 Data rate (max) (Mbps) 100 High input voltage (min) (V) 0.9 High input voltage (max) (V) 5.5 Vout (min) (V) 0.9 Vout (max) (V) 5.5 IOH (max) (mA) 0 IOL (max) (mA) 0 Supply current (max) (µA) 0.01 Features Output enable Input type Transmission Gate Output type 3-State, Transmission Gate Rating Automotive Operating temperature range (°C) -40 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 1: –40°C ≤ TA ≤ 125°C
    • Device HBM ESD classification level 2
    • CDM ESD classification level C6
  • Provides auto-bidirectional voltage translation without direction pin
  • Supports open drain or push-pull applications such as I2C, I2S, SPI, UART, JTAG, MDIO, SDIO, and GPIO
  • Supports up to 100-MHz up translation and greater than 100-MHz down translation at ≤ 30-pF capacitor load and up to 40-MHz up/down translation at 50-pF capacitor load
  • Supports Ioff, partial power down mode (see Section 7.3)
  • Allows bidirectional voltage level translation between
    • 0.95 V ↔ 1.8, 2.5, 3.3, 5.5 V
    • 1.2 V ↔ 1.8, 2.5, 3.3, 5.5 V
    • 1.8 V ↔ 2.5, 3.3, 5.5 V
    • 2.5 V ↔ 3.3, 5.5 V
    • 3.3 V ↔ 5.5 V
  • 5-V tolerance on I/O ports
  • Low Ron enables better signal integrity
  • Flow-through pinout for easy PCB trace routing
  • Latch-up performance exceeds 100 mA per JESD17
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 1: –40°C ≤ TA ≤ 125°C
    • Device HBM ESD classification level 2
    • CDM ESD classification level C6
  • Provides auto-bidirectional voltage translation without direction pin
  • Supports open drain or push-pull applications such as I2C, I2S, SPI, UART, JTAG, MDIO, SDIO, and GPIO
  • Supports up to 100-MHz up translation and greater than 100-MHz down translation at ≤ 30-pF capacitor load and up to 40-MHz up/down translation at 50-pF capacitor load
  • Supports Ioff, partial power down mode (see Section 7.3)
  • Allows bidirectional voltage level translation between
    • 0.95 V ↔ 1.8, 2.5, 3.3, 5.5 V
    • 1.2 V ↔ 1.8, 2.5, 3.3, 5.5 V
    • 1.8 V ↔ 2.5, 3.3, 5.5 V
    • 2.5 V ↔ 3.3, 5.5 V
    • 3.3 V ↔ 5.5 V
  • 5-V tolerance on I/O ports
  • Low Ron enables better signal integrity
  • Flow-through pinout for easy PCB trace routing
  • Latch-up performance exceeds 100 mA per JESD17

The LSF0204-Q1 is automotive qualified four channel auto bidirectional voltage translator that operate from 0.8 V to 4.5 V (Vref_A) and 1.8 V to 5.5 V (Vref_B). This range allows for bidirectional voltage translations between 0.8 V and 5.5 V without the need for a direction pin.

When the An or Bn port is LOW, the switch is in the ON-state and a low resistance connection exists between the An and Bn ports. The low Ron of the switch allows connections to be made with minimal propagation delay and minimal signal distortion. The voltage on the A or B side will be limited to Vref_A and can be pulled up to any level between Vref_A and 5.5 V

The supply voltage (VPUn) for each channel may be individually set up with a pull up resistor. For example, CH1 may be used in up-translation mode (1.2 V ↔ 3.3 V) and CH2 in down-translation mode (2.5 V ↔ 1.8 V).

When EN is HIGH, the translator switch is on, and the An I/O is connected to the Bn I/O, respectively, allowing bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state exists between ports. The EN input circuit is designed to be supplied by Vref_A. EN must be LOW to ensure the high-impedance state during power-up or power-down.

The LSF0204-Q1 is automotive qualified four channel auto bidirectional voltage translator that operate from 0.8 V to 4.5 V (Vref_A) and 1.8 V to 5.5 V (Vref_B). This range allows for bidirectional voltage translations between 0.8 V and 5.5 V without the need for a direction pin.

When the An or Bn port is LOW, the switch is in the ON-state and a low resistance connection exists between the An and Bn ports. The low Ron of the switch allows connections to be made with minimal propagation delay and minimal signal distortion. The voltage on the A or B side will be limited to Vref_A and can be pulled up to any level between Vref_A and 5.5 V

The supply voltage (VPUn) for each channel may be individually set up with a pull up resistor. For example, CH1 may be used in up-translation mode (1.2 V ↔ 3.3 V) and CH2 in down-translation mode (2.5 V ↔ 1.8 V).

When EN is HIGH, the translator switch is on, and the An I/O is connected to the Bn I/O, respectively, allowing bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state exists between ports. The EN input circuit is designed to be supplied by Vref_A. EN must be LOW to ensure the high-impedance state during power-up or power-down.

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Technical documentation

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* Data sheet LSF0204-Q1 Automotive Qualified 4-Bit Auto-Bidirectional Multi-Voltage Level Translator datasheet (Rev. B) PDF | HTML 29 Apr 2021
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Evaluation board

LSF-EVM — 1 to 8-bit LSF Translator Family Evaluation Module

The LSF family of devices are level translators that support a voltage range of 0.95V and 5V and provide multi-voltage bidirectional translation without a direction pin.

The LSF-EVM comes populated with the LSF0108PWR device and has landing patterns that are compatible with the LSF0101DRYR, (...)

User guide: PDF
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Simulation model

LSF0204 HSPICE Model

SLVMAL3.ZIP (7 KB) - HSpice Model
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TSSOP (PW) 14 View options

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