SLAS655E January 2010  – July 2015 MSP430F5418A , MSP430F5419A , MSP430F5435A , MSP430F5436A , MSP430F5437A , MSP430F5438A

PRODUCTION DATA. 

  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagrams
    2. 4.2Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6 Thermal Characteristics
    7. 5.7 Schmitt-Trigger Inputs - General-Purpose I/O
    8. 5.8 Inputs - Ports P1 and P2
    9. 5.9 Leakage Current - General-Purpose I/O
    10. 5.10Outputs - General-Purpose I/O (Full Drive Strength)
    11. 5.11Outputs - General-Purpose I/O (Reduced Drive Strength)
    12. 5.12Output Frequency - General-Purpose I/O
    13. 5.13Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16Crystal Oscillator, XT1, High-Frequency Mode
    17. 5.17Crystal Oscillator, XT2
    18. 5.18Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    19. 5.19Internal Reference, Low-Frequency Oscillator (REFO)
    20. 5.20DCO Frequency
    21. 5.21PMM, Brown-Out Reset (BOR)
    22. 5.22PMM, Core Voltage
    23. 5.23PMM, SVS High Side
    24. 5.24PMM, SVM High Side
    25. 5.25PMM, SVS Low Side
    26. 5.26PMM, SVM Low Side
    27. 5.27Wake-up Times From Low-Power Modes and Reset
    28. 5.28Timer_A
    29. 5.29Timer_B
    30. 5.30USCI (UART Mode) Recommended Operating Conditions
    31. 5.31USCI (UART Mode)
    32. 5.32USCI (SPI Master Mode) Recommended Operating Conditions
    33. 5.33USCI (SPI Master Mode)
    34. 5.34USCI (SPI Slave Mode)
    35. 5.35USCI (I2C Mode)
    36. 5.3612-Bit ADC, Power Supply and Input Range Conditions
    37. 5.3712-Bit ADC, Timing Parameters
    38. 5.3812-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
    39. 5.3912-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    40. 5.4012-Bit ADC, Temperature Sensor and Built-In VMID
    41. 5.41REF, External Reference
    42. 5.42REF, Built-In Reference
    43. 5.43Flash Memory
    44. 5.44JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1 CPU (Link to User's Guide)
    2. 6.2 Operating Modes
    3. 6.3 Interrupt Vector Addresses
    4. 6.4 Memory Organization
    5. 6.5 Bootstrap Loader (BSL)
    6. 6.6 JTAG Operation
      1. 6.6.1JTAG Standard Interface
      2. 6.6.2Spy-Bi-Wire Interface
    7. 6.7 Flash Memory (Link to User's Guide)
    8. 6.8 RAM Memory (Link to User's Guide)
    9. 6.9 Peripherals
      1. 6.9.1 Digital I/O (Link to User's Guide)
      2. 6.9.2 Oscillator and System Clock (Link to User's Guide)
      3. 6.9.3 Power Management Module (PMM) (Link to User's Guide)
      4. 6.9.4 Hardware Multiplier (MPY) (Link to User's Guide)
      5. 6.9.5 Real-Time Clock (RTC_A) (Link to User's Guide)
      6. 6.9.6 Watchdog Timer (WDT_A) (Link to User's Guide)
      7. 6.9.7 System Module (SYS) (Link to User's Guide)
      8. 6.9.8 DMA Controller (Link to User's Guide)
      9. 6.9.9 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      10. 6.9.10TA0 (Link to User's Guide)
      11. 6.9.11TA1 (Link to User's Guide)
      12. 6.9.12TB0 (Link to User's Guide)
      13. 6.9.13ADC12_A (Link to User's Guide)
      14. 6.9.14CRC16 (Link to User's Guide)
      15. 6.9.15REF Voltage Reference (Link to User's Guide)
      16. 6.9.16Embedded Emulation Module (EEM) (L Version) (Link to User's Guide)
      17. 6.9.17Peripheral File Map
    10. 6.10Input/Output Schematics
      1. 6.10.1 Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
      2. 6.10.2 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
      3. 6.10.3 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
      4. 6.10.4 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
      5. 6.10.5 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
      6. 6.10.6 Port P5, P5.2, Input/Output With Schmitt Trigger
      7. 6.10.7 Port P5, P5.3, Input/Output With Schmitt Trigger
      8. 6.10.8 Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger
      9. 6.10.9 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
      10. 6.10.10Port P7, P7.0, Input/Output With Schmitt Trigger
      11. 6.10.11Port P7, P7.1, Input/Output With Schmitt Trigger
      12. 6.10.12Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger
      13. 6.10.13Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
      14. 6.10.14Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
      15. 6.10.15Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
      16. 6.10.16Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger
      17. 6.10.17Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger
      18. 6.10.18Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      19. 6.10.19Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 6.11Device Descriptors (TLV)
  7. 7Device and Documentation Support
    1. 7.1Device Support
      1. 7.1.1Getting Started
      2. 7.1.2Development Tools Support
        1. 7.1.2.1Hardware Features
        2. 7.1.2.2Recommended Hardware Options
          1. 7.1.2.2.1Target Socket Boards
          2. 7.1.2.2.2Experimenter Boards
          3. 7.1.2.2.3Debugging and Programming Tools
          4. 7.1.2.2.4Production Programmers
        3. 7.1.2.3Recommended Software Options
          1. 7.1.2.3.1Integrated Development Environments
          2. 7.1.2.3.2MSP430Ware
          3. 7.1.2.3.3SYS/BIOS
          4. 7.1.2.3.4Command-Line Programmer
      3. 7.1.3Device and Development Tool Nomenclature
    2. 7.2Documentation Support
    3. 7.3Related Links
    4. 7.4Community Resources
    5. 7.5Trademarks
    6. 7.6Electrostatic Discharge Caution
    7. 7.7Export Control Notice
    8. 7.8Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

1 Device Overview

1.1 Features

  • Low Supply Voltage Range:
    3.6 V Down to 1.8 V
  • Ultra-Low Power Consumption
    • Active Mode (AM):
      All System Clocks Active
      230 µA/MHz at 8 MHz, 3.0 V, Flash Program Execution (Typical)
      110 µA/MHz at 8 MHz, 3.0 V, RAM Program Execution (Typical)
    • Standby Mode (LPM3):
      Real-Time Clock (RTC) With Crystal, Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wakeup:
      1.7 µA at 2.2 V, 2.1 µA at 3.0 V (Typical)
      Low-Power Oscillator (VLO), General-Purpose Counter, Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wakeup:
      1.2 µA at 3.0 V (Typical)
    • Off Mode (LPM4):
      Full RAM Retention, Supply Supervisor Operational, Fast Wakeup:
      1.2 µA at 3.0 V (Typical)
    • Shutdown Mode (LPM4.5):
      0.1 µA at 3.0 V (Typical)
  • Wake up From Standby Mode in 3.5 µs (Typical)
  • 16-Bit RISC Architecture
    • Extended Memory
    • Up to 25-MHz System Clock
  • Flexible Power-Management System
    • Fully Integrated LDO With Programmable Regulated Core Supply Voltage
    • Supply Voltage Supervision, Monitoring, and Brownout
  • Unified Clock System
    • FLL Control Loop for Frequency Stabilization
    • Low-Power Low-Frequency Internal Clock Source (VLO)
    • Low-Frequency Trimmed Internal Reference Source (REFO)
    • 32-kHz Crystals
    • High-Frequency Crystals up to 32 MHz
  • 16-Bit Timer TA0, Timer_A With Five Capture/Compare Registers
  • 16-Bit Timer TA1, Timer_A With Three Capture/Compare Registers
  • 16-Bit Timer TB0, Timer_B With Seven Capture/Compare Shadow Registers
  • Up to Four Universal Serial Communication Interfaces
    • USCI_A0, USCI_A1, USCI_A2, and USCI_A3 Each Support:
      • Enhanced UART Supports Automatic Baud-Rate Detection
      • IrDA Encoder and Decoder
      • Synchronous SPI
    • USCI_B0, USCI_B1, USCI_B2, and USCI_B3 Each Support:
      • I2C
      • Synchronous SPI
  • 12-Bit Analog-to-Digital Converter (ADC)
    • Internal Reference
    • Sample-and-Hold
    • Autoscan Feature
    • 14 External Channels, 2 Internal Channels
  • Hardware Multiplier Supports 32-Bit Operations
  • Serial Onboard Programming, No External Programming Voltage Needed
  • Three-Channel Internal DMA
  • Basic Timer With RTC Feature
  • Section 3 Summarizes the Available Family Members
  • For Complete Module Descriptions, See the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208)

1.2 Applications

  • Analog and Digital Sensor Systems
  • Digital Motor Controls
  • Remote Controls
  • Thermostats
  • Digital Timers
  • Hand-Held Meters

1.3 Description

The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with extensive low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in 3.5 µs (typical).

The MSP430F543xA and MSP430F541xA series are microcontroller configurations with three 16-bit timers, a high-performance 12-bit ADC, up to four universal serial communication interfaces (USCIs), a hardware multiplier, DMA, an RTC module with alarm capabilities, and up to 87 I/O pins.

Typical applications for this device include analog and digital sensor systems, digital motor control, remote controls, thermostats, digital timers, and hand-held meters.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE(2)
MSP430F5438AZQWMicroStar Junior™ BGA (113)7 mm × 7 mm
MSP430F5438APZLQFP (100)14 mm × 14 mm
MSP430F5437APNLQFP (80)12 mm × 12 mm
(1) For the most current part, package, and ordering information, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 8.

1.4 Functional Block Diagrams

Figure 1-1 and Figure 1-2 show the functional block diagrams.

MSP430F5438A MSP430F5437A MSP430F5436A MSP430F5435A MSP430F5419A MSP430F5418A slas655-fbd_38_36_19.gifFigure 1-1 Functional Block Diagram – MSP430F5438AIPZ, MSP430F5436AIPZ, MSP430F5419AIPZ, MSP430F5438AIZQW, MSP430F5436AIZQW, MSP430F5419AIZQW
MSP430F5438A MSP430F5437A MSP430F5436A MSP430F5435A MSP430F5419A MSP430F5418A slas655-fbd_37_35_18.gifFigure 1-2 Functional Block Diagram – MSP430F5437AIPN, MSP430F5435AIPN, MSP430F5418AIPN