SLAS645J July 2009  – April 2015 MSP430F5500 , MSP430F5501 , MSP430F5502 , MSP430F5503 , MSP430F5504 , MSP430F5505 , MSP430F5506 , MSP430F5507 , MSP430F5508 , MSP430F5509 , MSP430F5510

PRODUCTION DATA. 

  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagrams
    2. 4.2Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6 Thermal Packaging Characteristics
    7. 5.7 Schmitt-Trigger Inputs - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI)
    8. 5.8 Inputs - Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 5.9 Leakage Current - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI)
    10. 5.10Outputs - General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    11. 5.11Outputs - General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    12. 5.12Output Frequency - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    13. 5.13Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16Crystal Oscillator, XT2
    17. 5.17Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 5.18Internal Reference, Low-Frequency Oscillator (REFO)
    19. 5.19DCO Frequency
    20. 5.20PMM, Brown-Out Reset (BOR)
    21. 5.21PMM, Core Voltage
    22. 5.22PMM, SVS High Side
    23. 5.23PMM, SVM High Side
    24. 5.24PMM, SVS Low Side
    25. 5.25PMM, SVM Low Side
    26. 5.26Wake-up Times From Low-Power Modes and Reset
    27. 5.27Timer_A
    28. 5.28Timer_B
    29. 5.29USCI (UART Mode) Recommended Operating Conditions
    30. 5.30USCI (UART Mode)
    31. 5.31USCI (SPI Master Mode) Recommended Operating Conditions
    32. 5.32USCI (SPI Master Mode)
    33. 5.33USCI (SPI Slave Mode)
    34. 5.34USCI (I2C Mode)
    35. 5.3510-Bit ADC, Power Supply and Input Range Conditions
    36. 5.3610-Bit ADC, Timing Parameters
    37. 5.3710-Bit ADC, Linearity Parameters
    38. 5.38REF, External Reference
    39. 5.39REF, Built-In Reference
    40. 5.40Comparator B
    41. 5.41Ports PU.0 and PU.1
    42. 5.42USB-Output Ports DP and DM
    43. 5.43USB-Input Ports DP and DM
    44. 5.44USB-PWR (USB Power System)
    45. 5.45USB-PLL (USB Phase Locked Loop)
    46. 5.46Flash Memory
    47. 5.47JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1 CPU (Link to User's Guide)
    2. 6.2 Operating Modes
    3. 6.3 Interrupt Vector Addresses
    4. 6.4 Memory Organization
    5. 6.5 Bootstrap Loader (BSL)
      1. 6.5.1USB BSL
      2. 6.5.2UART BSL
    6. 6.6 JTAG Operation
      1. 6.6.1JTAG Standard Interface
      2. 6.6.2Spy-Bi-Wire Interface
    7. 6.7 Flash Memory (Link to User's Guide)
    8. 6.8 RAM (Link to User's Guide)
    9. 6.9 Peripherals
      1. 6.9.1 Digital I/O (Link to User's Guide)
      2. 6.9.2 Port Mapping Controller (Link to User's Guide)
      3. 6.9.3 Oscillator and System Clock (Link to User's Guide)
      4. 6.9.4 Power-Management Module (PMM) (Link to User's Guide)
      5. 6.9.5 Hardware Multiplier (MPY) (Link to User's Guide)
      6. 6.9.6 Real-Time Clock (RTC_A) (Link to User's Guide)
      7. 6.9.7 Watchdog Timer (WDT_A) (Link to User's Guide)
      8. 6.9.8 System Module (SYS) (Link to User's Guide)
      9. 6.9.9 DMA Controller (Link to User's Guide)
      10. 6.9.10Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      11. 6.9.11TA0 (Link to User's Guide)
      12. 6.9.12TA1 (Link to User's Guide)
      13. 6.9.13TA2 (Link to User's Guide)
      14. 6.9.14TB0 (Link to User's Guide)
      15. 6.9.15Comparator_B (Link to User's Guide)
      16. 6.9.16ADC10_A (Link to User's Guide)
      17. 6.9.17CRC16 (Link to User's Guide)
      18. 6.9.18Reference (REF) Voltage Reference (Link to User's Guide)
      19. 6.9.19Universal Serial Bus (USB) (Link to User's Guide)
      20. 6.9.20Embedded Emulation Module (EEM) (S Version) (Link to User's Guide)
    10. 6.10Peripheral File Map
    11. 6.11Input/Output Schematics
      1. 6.11.1 Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
      2. 6.11.2 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
      3. 6.11.3 Port P3, P3.0 to P3.4, Input/Output With Schmitt Trigger
      4. 6.11.4 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
      5. 6.11.5 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
      6. 6.11.6 Port P5, P5.2, Input/Output With Schmitt Trigger
      7. 6.11.7 Port P5, P5.3, Input/Output With Schmitt Trigger
      8. 6.11.8 Port P5, P5.4 and P5.5 Input/Output With Schmitt Trigger
      9. 6.11.9 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
      10. 6.11.10Port PU.0/DP, PU.1/DM, PUR USB Ports
      11. 6.11.11Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output
      12. 6.11.12Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    12. 6.12Device Descriptors
  7. 7Device and Documentation Support
    1. 7.1Device Support
      1. 7.1.1Getting Started
      2. 7.1.2Development Tools Support
        1. 7.1.2.1Hardware Features
        2. 7.1.2.2Recommended Hardware Options
          1. 7.1.2.2.1Target Socket Boards
          2. 7.1.2.2.2Experimenter Boards
          3. 7.1.2.2.3Debugging and Programming Tools
          4. 7.1.2.2.4Production Programmers
        3. 7.1.2.3Recommended Software Options
          1. 7.1.2.3.1Integrated Development Environments
          2. 7.1.2.3.2MSP430Ware
          3. 7.1.2.3.3MSP430 USB Developer's Package
          4. 7.1.2.3.4Command-Line Programmer
      3. 7.1.3Device and Development Tool Nomenclature
    2. 7.2Documentation Support
    3. 7.3Related Links
    4. 7.4Community Resources
    5. 7.5Trademarks
    6. 7.6Electrostatic Discharge Caution
    7. 7.7Export Control Notice
    8. 7.8Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

1 Device Overview

1.1 Features

  • Low Supply-Voltage Range:
    3.6 V Down to 1.8 V
  • Ultra-Low-Power Consumption
    • Active Mode (AM)
      All System Clocks Active
      • 195 µA/MHz at 8 MHz, 3 V, Flash Program Execution (Typical)
      • 115 µA/MHz at 8 MHz, 3 V, RAM Program Execution (Typical)
    • Standby Mode (LPM3)
      • Real-Time Clock (RTC) With Crystal, Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wakeup:
        1.9 µA at 2.2 V, 2.1 µA at 3 V (Typical)
      • Low-Power Oscillator (VLO), General-Purpose Counter, Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wakeup:
        1.4 µA at 3 V (Typical)
    • Off Mode (LPM4)
      Full RAM Retention, Supply Supervisor Operational, Fast Wakeup:
      1.1 µA at 3 V (Typical)
    • Shutdown Mode (LPM4.5)
      0.18 µA at 3 V (Typical)
  • Wakeup From Standby in Less Than 5 µs
  • 16-Bit RISC Architecture, Extended Memory, up to 25-MHz System Clock
  • Flexible Power-Management System
    • Fully Integrated LDO With Programmable Regulated Core Supply Voltage
    • Supply Voltage Supervision, Monitoring, and Brownout
  • Unified Clock System
    • FLL Control Loop for Frequency Stabilization
    • Low-Power Low-Frequency Internal Clock Source (VLO)
    • Low-Frequency Trimmed Internal Reference Source (REFO)
    • 32-kHz Watch Crystals (XT1)
    • High-Frequency Crystals up to 32 MHz (XT2)
  • 16-Bit Timer TA0, Timer_A With Five Capture/Compare Registers
  • 16-Bit Timer TA1, Timer_A With Three Capture/Compare Registers
  • 16-Bit Timer TA2, Timer_A With Three Capture/Compare Registers
  • 16-Bit Timer TB0, Timer_B With Seven Capture/Compare Shadow Registers
  • Two Universal Serial Communication Interfaces (USCIs)
    • USCI_A0 and USCI_A1 Each Support:
      • Enhanced UART Supports Auto-Baudrate Detection
      • IrDA Encoder and Decoder
      • Synchronous SPI
    • USCI_B0 and USCI_B1 Each Support:
      • I2C
      • Synchronous SPI
  • Full-Speed Universal Serial Bus (USB)
    • Integrated USB-PHY
    • Integrated 3.3-V and 1.8-V USB Power System
    • Integrated USB-PLL
    • Eight Input and Eight Output Endpoints
  • 10-Bit Analog-to-Digital Converter (ADC) With Window Comparator
  • Comparator
  • Hardware Multiplier Supports 32-Bit Operations
  • Serial Onboard Programming, No External Programming Voltage Needed
  • Three-Channel Internal DMA
  • Basic Timer With RTC Feature
  • Section 3 Summarizes Family Members
  • For Complete Module Descriptions, See the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208)

1.2 Applications

  • Analog and Digital Sensor Systems
  • Data Loggers
  • Connectivity to USB Hosts
  • Wireless Headsets

1.3 Description

The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with extensive low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in less than 5 µs.

The MSP430F5510, MSP430F5509, and MSP430F5508 devices are microcontroller configurations with integrated USB and PHY supporting USB 2.0, four 16-bit timers, a high-performance 10-bit analog-to-digital converter (ADC), two universal serial communication interfaces (USCIs)

(1) In the 48-pin packages, the USCI functions that are pinned out are limited to what the user configures on port 4 with the port mapping controller. It may not be possible to bring out all functions simultaneously.
, a hardware multiplier, DMA, a real-time clock (RTC) module with alarm capabilities, and 31 or 47 I/O pins.

The MSP430F5507, MSP430F5506, MSP430F5505, and MSP430F5504 devices are microcontroller configurations with integrated USB and PHY supporting USB 2.0, four 16-bit timers, a high-performance 10-bit ADC, one USCI, a hardware multiplier, DMA, an RTC module with alarm capabilities, and 31 I/O pins.

The MSP430F5503, MSP430F5502, MSP430F5501, and MSP430F5500 devices include all of the MSP430F5507, MSP430F5506, MSP430F5505, and MSP430F5504 peripherals, except that they have a comparator instead of the 10-bit ADC.

Typical applications include analog and digital sensor systems and data loggers that require connectivity to various USB hosts.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE(2)
MSP430F5510RGCVQFN (64)9 mm × 9 mm
MSP430F5510ZQEBGA (80)5 mm × 5 mm
MSP430F5510PTLQFP (48) 7 mm × 7 mm
MSP430F5510RGZ VQFN (48) 7 mm × 7 mm
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 8.

1.4 Functional Block Diagrams

Figure 1-1 shows the functional block diagram for the MSP430F5510, MSP430F5509, and MSP430F5508 devices in the RGC and ZQE packages.

MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 slas645_block64pin.gifFigure 1-1 Functional Block Diagram – MSP430F5510IRGC, MSP430F5509IRGC, MSP430F5508IRGC, MSP430F5510IZQE, MSP430F5509IZQE, MSP430F5508IZQE

Figure 1-2 shows the functional block diagram for the MSP430F5510, MSP430F5509, and MSP430F5508 devices in the RGZ and PT packages.

MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 slas645_block48pin.gif
A.

NOTE:

See Table 3-1 for limitations on the simultaneous availability of USCI module signals.
Figure 1-2 Functional Block Diagram – MSP430F5510IRGZ, MSP430F5509IRGZ, MSP430F5508IRGZ, MSP430F5510IPT, MSP430F5509IPT, MSP430F5508IPT

Figure 1-3 shows the functional block diagram for the MSP430F5507, MSP430F5506, and MSP430F5505 devices in the RGZ package and the MSP430F5504 device in the RGZ and PT packages.

MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 slas645_block48pin_no_comp.gifFigure 1-3 Functional Block Diagram – MSP430F5507IRGZ, MSP430F5506IRGZ, MSP430F5505IRGZ, MSP430F5504IRGZ, MSP430F5504IPT

Figure 1-4 shows the functional block diagram for the MSP430F5503, MSP430F5502, MSP430F5501, and MSP430F5500 devices in the RGZ package.

MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 slas645_block48pin_no_ADC10.gifFigure 1-4 Functional Block Diagram – MSP430F5503IRGZ, MSP430F5502IRGZ, MSP430F5501IRGZ, MSP430F5500IRGZ