SLAS566E June 2010  – December 2015 MSP430F6630 , MSP430F6631 , MSP430F6632 , MSP430F6633 , MSP430F6634 , MSP430F6635 , MSP430F6636 , MSP430F6637 , MSP430F6638


  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Designation - MSP430F6638IPZ, MSP430F6637IPZ, MSP430F6636IPZ
    2. 4.2Pin Designation - MSP430F6635IPZ, MSP430F6634IPZ, MSP430F6633IPZ
    3. 4.3Pin Designation - MSP430F6632IPZ, MSP430F6631IPZ, MSP430F6630IPZ
    4. 4.4Pin Designation - MSP430F6638IZQW, MSP430F6637IZQW, MSP430F6636IZQW, MSP430F6635IZQW, MSP430F6634IZQW, MSP430F6633IZQW, MSP430F6632IZQW, MSP430F6631IZQW, MSP430F6630IZQW
    5. 4.5Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 5.7 Thermal Resistance Characteristics
    8. 5.8 Schmitt-Trigger Inputs - General-Purpose I/O
    9. 5.9 Inputs - Ports P1, P2, P3, and P4
    10. 5.10Leakage Current - General-Purpose I/O
    11. 5.11Outputs - General-Purpose I/O (Full Drive Strength)
    12. 5.12Outputs - General-Purpose I/O (Reduced Drive Strength)
    13. 5.13Output Frequency - Ports P1, P2, and P3
    14. 5.14Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
    15. 5.15Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
    16. 5.16Crystal Oscillator, XT1, Low-Frequency Mode
    17. 5.17Crystal Oscillator, XT2
    18. 5.18Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    19. 5.19Internal Reference, Low-Frequency Oscillator (REFO)
    20. 5.20DCO Frequency
    21. 5.21PMM, Brownout Reset (BOR)
    22. 5.22PMM, Core Voltage
    23. 5.23PMM, SVS High Side
    24. 5.24PMM, SVM High Side
    25. 5.25PMM, SVS Low Side
    26. 5.26PMM, SVM Low Side
    27. 5.27Wake-up Times From Low-Power Modes and Reset
    28. 5.28Timer_A, Timers TA0, TA1, and TA2
    29. 5.29Timer_B, Timer TB0
    30. 5.30Battery Backup
    31. 5.31USCI (UART Mode)
    32. 5.32USCI (SPI Master Mode)
    33. 5.33USCI (SPI Slave Mode)
    34. 5.34USCI (I2C Mode)
    35. 5.35LCD_B, Recommended Operating Conditions
    36. 5.36LCD_B, Electrical Characteristics
    37. 5.3712-Bit ADC, Power Supply and Input Range Conditions
    38. 5.3812-Bit ADC, Timing Parameters
    39. 5.3912-Bit ADC, Linearity Parameters Using an External Reference Voltage
    40. 5.4012-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage
    41. 5.4112-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    42. 5.4212-Bit ADC, Temperature Sensor and Built-In VMID
    43. 5.43REF, External Reference
    44. 5.44REF, Built-In Reference
    45. 5.4512-Bit DAC, Supply Specifications
    46. 5.4612-Bit DAC, Linearity Specifications
    47. 5.4712-Bit DAC, Output Specifications
    48. 5.4812-Bit DAC, Reference Input Specifications
    49. 5.4912-Bit DAC, Dynamic Specifications
    50. 5.5012-Bit DAC, Dynamic Specifications (Continued)
    51. 5.51Comparator_B
    52. 5.52Ports PU.0 and PU.1
    53. 5.53USB Output Ports DP and DM
    54. 5.54USB Input Ports DP and DM
    55. 5.55USB-PWR (USB Power System)
    56. 5.56USB-PLL (USB Phase-Locked Loop)
    57. 5.57Flash Memory
    58. 5.58JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 CPU
    3. 6.3 Instruction Set
    4. 6.4 Operating Modes
    5. 6.5 Interrupt Vector Addresses
    6. 6.6 Memory
    7. 6.7 Bootloader (BSL)
      1. 6.7.1USB BSL
      2. 6.7.2UART BSL
    8. 6.8 JTAG Operation
      1. 6.8.1JTAG Standard Interface
      2. 6.8.2Spy-Bi-Wire Interface
    9. 6.9 Flash Memory (Link to User's Guide)
    10. 6.10RAM (Link to User's Guide)
    11. 6.11Backup RAM
    12. 6.12Peripherals
      1. 6.12.1 Digital I/O (Link to User's Guide)
      2. 6.12.2 Port Mapping Controller (Link to User's Guide)
      3. 6.12.3 Oscillator and System Clock (Link to User's Guide)
      4. 6.12.4 Power-Management Module (PMM) (Link to User's Guide)
      5. 6.12.5 Hardware Multiplier (MPY) (Link to User's Guide)
      6. 6.12.6 Real-Time Clock (RTC_B) (Link to User's Guide)
      7. 6.12.7 Watchdog Timer (WDT_A) (Link to User's Guide)
      8. 6.12.8 System Module (SYS) (Link to User's Guide)
      9. 6.12.9 DMA Controller (Link to User's Guide)
      10. 6.12.10Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      11. 6.12.11Timer TA0 (Link to User's Guide)
      12. 6.12.12Timer TA1 (Link to User's Guide)
      13. 6.12.13Timer TA2 (Link to User's Guide)
      14. 6.12.14Timer TB0 (Link to User's Guide)
      15. 6.12.15Comparator_B (Link to User's Guide)
      16. 6.12.16ADC12_A (Link to User's Guide)
      17. 6.12.17DAC12_A (Link to User's Guide)
      18. 6.12.18CRC16 (Link to User's Guide)
      19. 6.12.19Voltage Reference (REF) Module (Link to User's Guide)
      20. 6.12.20LCD_B (Link to User's Guide)
      21. 6.12.21USB Universal Serial Bus (Link to User's Guide)
      22. 6.12.22Embedded Emulation Module (EEM) (Link to User's Guide)
      23. 6.12.23Peripheral File Map
    13. 6.13Input/Output Schematics
      1. 6.13.1 Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
      2. 6.13.2 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
      3. 6.13.3 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
      4. 6.13.4 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
      5. 6.13.5 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
      6. 6.13.6 Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger
      7. 6.13.7 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
      8. 6.13.8 Port P7, P7.2, Input/Output With Schmitt Trigger
      9. 6.13.9 Port P7, P7.3, Input/Output With Schmitt Trigger
      10. 6.13.10Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
      11. 6.13.11Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
      12. 6.13.12Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
      13. 6.13.13Port PU.0/DP, PU.1/DM, PUR USB Ports
      14. 6.13.14Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      15. 6.13.15Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    14. 6.14Device Descriptors
  7. 7Device and Documentation Support
    1. 7.1Device Support
      1. 7.1.1Development Support
        1. Started and Next Steps
        2. Tools Support
          1. Features
          2. Hardware Options
            1. Socket Boards
            2. Boards
            3. and Programming Tools
            4. Programmers
          3. Software Options
            1. Development Environments
            4. USB Developer's Package
            5. Programmer
      2. 7.1.2Device and Development Tool Nomenclature
    2. 7.2Documentation Support
    3. 7.3Related Links
    4. 7.4Community Resources
    5. 7.5Trademarks
    6. 7.6Electrostatic Discharge Caution
    7. 7.7Export Control Notice
    8. 7.8Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

1 Device Overview

1.1 Features

  • Low Supply Voltage Range: 1.8 V to 3.6 V
  • Ultra-Low Power Consumption
    • Active Mode (AM):
      All System Clocks Active:
      270 µA/MHz at 8 MHz, 3.0 V, Flash Program Execution (Typical)
    • Standby Mode (LPM3):
      Watchdog With Crystal and Supply Supervisor Operational, Full RAM Retention, Fast Wakeup:
      1.8 µA at 2.2 V, 2.1 µA at 3.0 V (Typical)
    • Shutdown Real-Time Clock (RTC) Mode (LPM3.5):
      Shutdown Mode, Active RTC With Crystal:
      1.1 µA at 3.0 V (Typical)
    • Shutdown Mode (LPM4.5):
      0.3 µA at 3.0 V (Typical)
  • Wake up From Standby Mode in 3 µs (Typical)
  • 16-Bit RISC Architecture, Extended Memory, up to 20-MHz System Clock
  • Flexible Power-Management System
    • Fully Integrated LDO With Programmable Regulated Core Supply Voltage
    • Supply Voltage Supervision, Monitoring, and Brownout
  • Unified Clock System
    • FLL Control Loop for Frequency Stabilization
    • Low-Power Low-Frequency Internal Clock Source (VLO)
    • Low-Frequency Trimmed Internal Reference Source (REFO)
    • 32-kHz Crystals (XT1)
    • High-Frequency Crystals up to 32 MHz (XT2)
  • Four 16-Bit Timers With 3, 5, or 7 Capture/Compare Registers
  • Two Universal Serial Communication Interfaces (USCIs)
    • USCI_A0 and USCI_A1 Each Support:
      • Enhanced UART Supports Automatic Baud-Rate Detection
      • IrDA Encoder and Decoder
      • Synchronous SPI
    • USCI_B0 and USCI_B1 Each Support:
      • I2C
      • Synchronous SPI
  • Full-Speed Universal Serial Bus (USB)
    • Integrated USB-PHY
    • Integrated 3.3-V and 1.8-V USB Power System
    • Integrated USB-PLL
    • Eight Input and Eight Output Endpoints
  • 12-Bit Analog-to-Digital Converter (ADC) With Internal Shared Reference, Sample-and-Hold, and Autoscan Feature
  • Dual 12-Bit Digital-to-Analog Converters (DACs) With Synchronization
  • Voltage Comparator
  • Integrated Liquid Crystal Display (LCD) Driver With Contrast Control for up to 160 Segments
  • Hardware Multiplier Supports 32-Bit Operations
  • Serial Onboard Programming, No External Programming Voltage Needed
  • Six-Channel Internal DMA
  • RTC Module With Supply Voltage Backup Switch
  • Table 3-1 Summarizes the Available Family Members
  • For Complete Module Descriptions, See the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208)

1.2 Applications

  • Analog and Digital Sensor Systems
  • Digital Motor Control
  • Remote Controls
  • Thermostats
  • Digital Timers
  • Hand-Held Meters

1.3 Description

The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in 3 µs (typical).

The MSP430F663x devices are microcontrollers with a high-performance 12-bit ADC, a comparator, two USCIs, USB 2.0, a hardware multiplier, DMA, four 16-bit timers, an RTC module with alarm capabilities, an LCD driver, and up to 74 I/O pins.

Device Information(1)

MSP430F6638IPZLQFP (100)14 mm × 14 mm
MSP430F6638IZQWBGA (113)7 mm × 7 mm
(1) For the most current device, package, and ordering information, see the Package Option Addendum in Section 8, or see the TI website at
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 8.

1.4 Functional Block Diagrams

Figure 1-1 shows the functional block diagram for the MSP430F6638, MSP430F6637, and MSP430F6636 devices.

MSP430F6638 MSP430F6637 MSP430F6636 MSP430F6635 MSP430F6634 MSP430F6633 MSP430F6632 MSP430F6631 MSP430F6630 slas566-fbd-f6638_WITHOUT-EDI.gif Figure 1-1 Functional Block Diagram – MSP430F6638, MSP430F6637, MSP430F6636

Figure 1-2 shows the functional block diagram for the MSP430F6635, MSP430F6634, and MSP430F6633 devices.

MSP430F6638 MSP430F6637 MSP430F6636 MSP430F6635 MSP430F6634 MSP430F6633 MSP430F6632 MSP430F6631 MSP430F6630 slas566-fbd-f6635_WITHOUT-EDI.gif Figure 1-2 Functional Block Diagram – MSP430F6635, MSP430F6634, MSP430F6633

Figure 1-3 shows the functional block diagram for the MSP430F6632, MSP430F6631, and MSP430F6630 devices.

MSP430F6638 MSP430F6637 MSP430F6636 MSP430F6635 MSP430F6634 MSP430F6633 MSP430F6632 MSP430F6631 MSP430F6630 slas566-fbd-f6632_WITHOUT-EDI.gif Figure 1-3 Functional Block Diagram – MSP430F6632, MSP430F6631, MSP430F6630