SLASE78B August 2016  – July 2017 MSP430FR2000 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111


  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagrams
    2. 4.2Pin Attributes
    3. 4.3Signal Descriptions
    4. 4.4Pin Multiplexing
    5. 4.5Connection of Unused Pins
    6. 4.6Buffer Type
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5 Active Mode Supply Current Per MHz
    6. 5.6 Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7 Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8 Typical Characteristics - LPM3 Supply Currents
    9. 5.9 Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    10. 5.10Typical Characteristics - LPMx.5 Supply Currents
    11. 5.11Typical Characteristics - Current Consumption Per Module
    12. 5.12Thermal Resistance Characteristics
    13. 5.13Timing and Switching Characteristics
      1. 5.13.1 Power Supply Sequencing
      2. 5.13.2 Reset Timing
      3. 5.13.3 Clock Specifications
      4. 5.13.4 Digital I/Os
        1. I/O Typical Characteristics
      5. 5.13.5 VREF+ Built-in Reference
      6. 5.13.6 Timer_B
      7. 5.13.7 eUSCI
      8. 5.13.8 ADC
      9. 5.13.9 Enhanced Comparator (eCOMP)
      10. 5.13.10FRAM
      11. 5.13.11Emulation and Debug
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 CPU
    3. 6.3 Operating Modes
    4. 6.4 Interrupt Vector Addresses
    5. 6.5 Memory Organization
    6. 6.6 Bootloader (BSL)
    7. 6.7 JTAG Standard Interface
    8. 6.8 Spy-Bi-Wire Interface (SBW)
    9. 6.9 FRAM
    10. 6.10Memory Protection
    11. 6.11Peripherals
      1. 6.11.1 Power-Management Module (PMM) and On-Chip Reference Voltages
      2. 6.11.2 Clock System (CS) and Clock Distribution
      3. 6.11.3 General-Purpose Input/Output Port (I/O)
      4. 6.11.4 Watchdog Timer (WDT)
      5. 6.11.5 System Module (SYS)
      6. 6.11.6 Cyclic Redundancy Check (CRC)
      7. 6.11.7 Enhanced Universal Serial Communication Interface (eUSCI_A0)
      8. 6.11.8 Timers (Timer0_B3)
      9. 6.11.9 Backup Memory (BAKMEM)
      10. 6.11.10Real-Time Clock (RTC) Counter
      11. 6.11.1110-Bit Analog-to-Digital Converter (ADC)
      12. 6.11.12eCOMP0
      13. 6.11.13Embedded Emulation Module (EEM)
      14. 6.11.14Peripheral File Map
      15. 6.11.15Input/Output Diagrams
        1. P1 Input/Output With Schmitt Trigger
        2. P2 Input/Output With Schmitt Trigger
    12. 6.12Device Descriptors (TLV)
    13. 6.13Identification
      1. 6.13.1Revision Identification
      2. 6.13.2Device Identification
      3. 6.13.3JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1Device Connection and Layout Fundamentals
      1. 7.1.1Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2External Oscillator
      3. 7.1.3JTAG
      4. 7.1.4Reset
      5. 7.1.5Unused Pins
      6. 7.1.6General Layout Recommendations
      7. 7.1.7Do's and Don'ts
    2. 7.2Peripheral- and Interface-Specific Design Information
      1. 7.2.1ADC Peripheral
        1. Schematic
        2. Requirements
        3. Guidelines
    3. 7.3Typical Applications
  8. 8Device and Documentation Support
    1. 8.1Getting Started and Next Steps
    2. 8.2Device Nomenclature
    3. 8.3Tools and Software
    4. 8.4Documentation Support
    5. 8.5Related Links
    6. 8.6Community Resources
    7. 8.7Trademarks
    8. 8.8Electrostatic Discharge Caution
    9. 8.9Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Device Overview


  • Embedded Microcontroller
    • 16-Bit RISC Architecture up to 16 MHz
    • Wide Supply Voltage Range (1.8 V to 3.6 V) (1)
  • Optimized Low-Power Modes (at 3 V)
    • Active Mode: 120 µA/MHz
    • Standby
      • LPM3.5 With VLO: 1 µA
      • Real-Time Clock (RTC) Counter (LPM3.5 With 32768-Hz Crystal): 1 µA
    • Shutdown (LPM4.5): 34 nA Without SVS
  • High-Performance Analog
    • 8-Channel 10-Bit Analog-to-Digital Converter (ADC)
      • Integrated Temperature Sensor
      • Internal 1.5-V Reference
      • Sample-and-Hold 200 ksps
    • Enhanced Comparator (eCOMP)
      • Integrated 6-Bit DAC as Reference Voltage
      • Programmable Hysteresis
      • Configurable High-Power and Low-Power Modes
  • Low-Power Ferroelectric RAM (FRAM)
    • Up to 3.75KB of Nonvolatile Memory
    • Built-In Error Correction Code (ECC)
    • Configurable Write Protection
    • Unified Memory of Program, Constants, and Storage
    • 1015 Write Cycle Endurance
    • Radiation Resistant and Nonmagnetic
  • Intelligent Digital Peripherals
    • One 16-Bit Timer With Three Capture/Compare Registers (Timer_B3)
    • One 16-Bit Counter-Only RTC Counter
    • 16-Bit Cyclic Redundancy Checker (CRC)
  • Enhanced Serial Communications
    • Enhanced USCI A (eUSCI_A) Supports UART, IrDA, and SPI
  • Clock System (CS)
    • On-Chip 32-kHz RC Oscillator (REFO)
    • On-Chip 16-MHz Digitally Controlled Oscillator (DCO) With Frequency-Locked Loop (FLL)
      • ±1% Accuracy With On-Chip Reference at Room Temperature
    • On-Chip Very-Low-Frequency 10-kHz Oscillator (VLO)
    • On-Chip High-Frequency Modulation Oscillator (MODOSC)
    • External 32-kHz Crystal Oscillator (LFXT)
    • Programmable MCLK Prescalar of 1 to 128
    • SMCLK Derived From MCLK With Programmable Prescalar of 1, 2, 4, or 8
  • General Input/Output and Pin Functionality
    • 12 I/Os on 16-Pin Package
    • 8 Interrupt Pins (4 Pins of P1 and 4 Pins of P2) Can Wake MCU From LPMs
    • All I/Os are Capacitive Touch I/Os
  • Development Tools and Software (Also See Tools and Software)
  • Family Members (Also See Device Comparison)
    • MSP430FR2111: 3.75KB of Program FRAM + 1KB of RAM
    • MSP430FR2110: 2KB of Program FRAM + 1KB of RAM
    • MSP430FR2100: 1KB of Program FRAM + 512 Bytes of RAM
    • MSP430FR2000: 0.5KB of Program FRAM + 512 Bytes of RAM
  • Package Options
    • 16-Pin: TSSOP (PW16)
    • 24-Pin: VQFN (RLL)
  • For Complete Module Descriptions, See the MSP430FR4xx and MSP430FR2xx Family User's Guide
Operation voltage is restricted by SVS levels (see V
Operation voltage is restricted by SVS levels (see VSVSH– and VSVSH+ in Power Supply Sequencing).


  • Appliance Battery Packs
  • Smoke and Heat Detectors
  • Door and Window Sensors
  • Lighting Sensors
  • Power Monitoring
  • Personal Care Electronics Portable
  • Health and Fitness Devices


MSP430FR2000 and MSP430FR21xx devices are part of the MSP430™ microcontroller (MCU) value line sensing portfolio. This ultra-low-power, low-cost MCU family offers memory sizes from 0.5KB to 4KB of FRAM unified memory with several package options including a small 3-mm×3-mm VQFN package. The architecture, FRAM, and integrated peripherals, combined with extensive low-power modes, are optimized to achieve extended battery life in portable, battery-powered sensing applications. MSP430FR2000 and MSP430FR21xx devices offer a migration path for 8-bit designs to gain additional features and functionality from peripheral integration and the data-logging and low-power benefits of FRAM. Additionally, existing designs using MSP430G2x MCUs can migrate to the MSP430FR2000 and MSP430F21xx family to increase performance and get the benefits of FRAM.

The MSP430FR2000 and MSP430FR21xx MCUs feature a powerful 16-bit RISC CPU, 16-bit registers, and a constant generator that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) also allows the device to wake up from low-power modes to active mode typically in less than 10 μs. The feature set of this MCU meets the needs of applications ranging from appliance battery packs and battery monitoring to smoke detectors and fitness accessories.

The MSP ultra-low-power (ULP) FRAM microcontroller platform combines uniquely embedded FRAM and a holistic ultra-low-power system architecture, allowing system designers to increase performance while lowering energy consumption. FRAM technology combines the low-energy fast writes, flexibility, and endurance of RAM with the nonvolatile behavior of flash.

MSP430FR2000 and MSP430FR21x MCUs are supported by an extensive hardware and software ecosystem with reference designs and code examples to get your design started quickly. Development kits include the MSP-EXP430FR2311 and MSP430FR4133 LaunchPad™ development kit and the MSP‑TS430PW20 20-pin target development board. TI also provides free MSP430Ware™ software, which is available as a component of Code Composer Studio™ IDE desktop and cloud versions within TI Resource Explorer. The MSP430 MCUs are also supported by extensive online collateral, training, and online support through the E2E™ Community Forum.

Device Information(1)

MSP430FR2111IPW16TSSOP (16)5 mm × 4.4 mm
MSP430FR2111IRLLVQFN (24)3 mm × 3 mm
For the most current part, package, and ordering information, see the Package Option Addendum in Section 9, or see the TI website at
The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 9.


System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical overstress or disturbing of data or code memory. See MSP430™ System-Level ESD Considerations for more information.

Functional Block Diagram

Figure 1-1 shows the functional block diagram.

MSP430FR2111 MSP430FR2110 MSP430FR2100 MSP430FR2000 Functional_Block_Diagram.gif


The ADC is not available on the MSP430FR2000 device.
Figure 1-1 Functional Block Diagram
  • The device has one main power pair of DVCC and DVSS that supplies both digital and analog modules. Recommended bypass and decoupling capacitors are 4.7 µF to 10 µF and 0.1 µF, respectively, with ±5% accuracy.
  • Four pins of P1 and four pins of P2 feature the pin-interrupt function and can wake the MCU from all LPMs, including LPM4, LPM3.5, and LPM4.5.
  • The Timer_B3 has three capture/compare registers. Only CCR1 and CCR2 are externally connected. CCR0 registers can be used only for internal period timing and interrupt generation.
  • In LPM3.5, the RTC counter and backup memory can be functional while the rest of peripherals are off.
  • All general-purpose I/Os can be configured as Capacitive Touch I/Os.