SLAS942B November 2015  – June 2017 MSP430FR2532 , MSP430FR2533 , MSP430FR2632 , MSP430FR2633

PRODUCTION DATA. 

  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagrams
    2. 4.2Pin Attributes
    3. 4.3Signal Descriptions
    4. 4.4Pin Multiplexing
    5. 4.5Buffer Types
    6. 4.6Connection of Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5 Active Mode Supply Current Per MHz
    6. 5.6 Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7 Low-Power Mode (LPM3 and LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8 Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9 Typical Characteristics - Low-Power Mode Supply Currents
    10. 5.10Thermal Resistance Characteristics
    11. 5.11Timing and Switching Characteristics
      1. 5.11.1 Power Supply Sequencing
      2. 5.11.2 Reset Timing
      3. 5.11.3 Clock Specifications
      4. 5.11.4 Digital I/Os
        1. 5.11.4.1Typical Characteristics - Outputs at 3 V and 2 V
      5. 5.11.5 VREF+ Built-in Reference
      6. 5.11.6 Timer_A
      7. 5.11.7 eUSCI
      8. 5.11.8 ADC
      9. 5.11.9 CapTIvate
      10. 5.11.10FRAM
      11. 5.11.11Debug and Emulation
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 CPU
    3. 6.3 Operating Modes
    4. 6.4 Interrupt Vector Addresses
    5. 6.5 Bootloader (BSL)
    6. 6.6 JTAG Standard Interface
    7. 6.7 Spy-Bi-Wire Interface (SBW)
    8. 6.8 FRAM
    9. 6.9 Memory Protection
    10. 6.10Peripherals
      1. 6.10.1 Power-Management Module (PMM)
      2. 6.10.2 Clock System (CS) and Clock Distribution
      3. 6.10.3 General-Purpose Input/Output Port (I/O)
      4. 6.10.4 Watchdog Timer (WDT)
      5. 6.10.5 System (SYS) Module
      6. 6.10.6 Cyclic Redundancy Check (CRC)
      7. 6.10.7 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.10.8 Timers (Timer0_A3, Timer1_A3, Timer2_A2 and Timer3_A2)
      9. 6.10.9 Hardware Multiplier (MPY)
      10. 6.10.10Backup Memory (BAKMEM)
      11. 6.10.11Real-Time Clock (RTC)
      12. 6.10.1210-Bit Analog-to-Digital Converter (ADC)
      13. 6.10.13CapTIvate
      14. 6.10.14Embedded Emulation Module (EEM)
    11. 6.11Input/Output Diagrams
      1. 6.11.1Port P1 Input/Output With Schmitt Trigger
      2. 6.11.2Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      3. 6.11.3Port P2 (P2.3 to P2.7) Input/Output With Schmitt Trigger
      4. 6.11.4Port P3 (P3.0 to P3.2) Input/Output With Schmitt Trigger
    12. 6.12Device Descriptors
    13. 6.13Memory
      1. 6.13.1Memory Organization
      2. 6.13.2Peripheral File Map
    14. 6.14Identification
      1. 6.14.1Revision Identification
      2. 6.14.2Device Identification
      3. 6.14.3JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1Device Connection and Layout Fundamentals
      1. 7.1.1Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2External Oscillator
      3. 7.1.3JTAG
      4. 7.1.4Reset
      5. 7.1.5Unused Pins
      6. 7.1.6General Layout Recommendations
      7. 7.1.7Do's and Don'ts
    2. 7.2Peripheral- and Interface-Specific Design Information
      1. 7.2.1ADC Peripheral
        1. 7.2.1.1Partial Schematic
        2. 7.2.1.2Design Requirements
        3. 7.2.1.3Layout Guidelines
      2. 7.2.2CapTIvate Peripheral
        1. 7.2.2.1Device Connection and Layout Fundamentals
          1. 7.2.2.1.1VREG
          2. 7.2.2.1.2ESD Protection
          3. 7.2.2.1.3Mutual- and Self-Capacitance
          4. 7.2.2.1.4Self-Capacitance
          5. 7.2.2.1.5Mutual Capacitance
        2. 7.2.2.2Measurements
          1. 7.2.2.2.1SNR
          2. 7.2.2.2.2Sensitivity
          3. 7.2.2.2.3Power
    3. 7.3Typical Applications
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Export Control Notice
    10. 8.10Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

Device Overview

Features

  • CapTIvate Technology – Capacitive Touch
    • Performance
      • Fast Electrode Scanning With Four Simultaneous Scans
      • Support for High-Resolution Sliders With >1024 Points
      • 30-cm Proximity Sensing
    • Reliability
      • Increased Immunity to Power Line, RF, and Other Environmental Noise
      • Built-in Spread Spectrum, Automatic Tuning, Noise Filtering, and Debouncing Algorithms
      • Enables Reliable Touch Solutions With 10-V RMS Common-Mode Noise, 4-kV Electrical Fast Transients, and 15-kV Electrostatic Discharge, Allowing for IEC‑61000-4-6, IEC-61000-4-4, and IEC‑61000-4-2 Compliance
      • Reduced RF Emissions to Simplify Electrical Designs
      • Support for Metal Touch and Water Rejection Designs
    • Flexibility
    • Low Power
      • <0.9 µA/Button in Wake-on-Touch Mode, Where Capacitive Measurement and Touch Detection is Done by Hardware State Machine While CPU is Asleep
      • Wake-on-Touch State Machine Allows Electrode Scanning While CPU is Asleep
      • Hardware Acceleration for Environmental Compensation, Filtering, and Threshold Detection
    • Ease of Use
      • CapTIvate Design Center, PC GUI Lets Engineers Design and Tune Capacitive Buttons in Real Time Without Having to Write Code
      • CapTIvate Software Library in ROM Provides Ample FRAM for Customer Application
  • Embedded Microcontroller
    • 16-Bit RISC Architecture
    • Clock Supports Frequencies up to 16 MHz
    • Wide Supply Voltage Range From 1.8 V to 3.6 V (1)
  • Optimized Ultra-Low-Power Modes
    • Active Mode: 126 µA/MHz (Typical)
    • Standby
      • 1.7 µA/Button Average (Typical) (16 Self-Capacitance Buttons, 8-Hz Scanning)
      • 1.7 µA/Button Average (Typical) (64 Mutual-Capacitance Buttons, 8-Hz Scanning)
    • LPM3.5 Real-Time Clock (RTC) Counter With 32768-Hz Crystal: 730 nA (Typical)
    • Shutdown (LPM4.5): 16 nA (Typical)
  • Low-Power Ferroelectric RAM (FRAM)
    • Up to 15.5KB of Nonvolatile Memory
    • Built-In Error Correction Code (ECC)
    • Configurable Write Protection
    • Unified Memory of Program, Constants, and Storage
    • 1015 Write Cycle Endurance
    • Radiation Resistant and Nonmagnetic
    • High FRAM-to-SRAM Ratio, up to 4:1
  • Intelligent Digital Peripherals
    • Four 16-Bit Timers
      • Two Timers With Three Capture/Compare Registers Each (Timer_A3)
      • Two Timers With Two Capture/Compare Registers Each (Timer_A2)
    • One 16-Bit Timer Associated With CapTIvate™ Technology
    • One 16-Bit Counter-Only RTC
    • 16-Bit Cyclic Redundancy Check (CRC)
  • Enhanced Serial Communications
    • Two Enhanced Universal Serial Communication Interfaces (eUSCI_A) Support UART, IrDA, and SPI
    • One eUSCI (eUSCI_B) Supports SPI and I2C
  • High-Performance Analog
    • 8-Channel 10-Bit Analog-to-Digital Converter (ADC)
      • Internal 1.5-V Reference
      • Sample-and-Hold 200 ksps
  • Clock System (CS)
    • On-Chip 32-kHz RC Oscillator (REFO)
    • On-Chip 16-MHz Digitally Controlled Oscillator (DCO) With Frequency-Locked Loop (FLL)
      • ±1% Accuracy With On-Chip Reference at Room Temperature
    • On-Chip Very Low-Frequency 10-kHz Oscillator (VLO)
    • On-Chip High-Frequency Modulation Oscillator (MODOSC)
    • External 32-kHz Crystal Oscillator (LFXT)
    • Programmable MCLK Prescalar of 1 to 128
    • SMCLK Derived from MCLK With Programmable Prescalar of 1, 2, 4, or 8
  • General Input/Output and Pin Functionality
    • Total of 19 I/Os on TSSOP-32 Package
    • 16 Interrupt Pins (P1 and P2) Can Wake MCU From Low-Power Modes
  • Development Tools and Software
    • Ease-of-Use Ecosystem
      • CapTIvate Design Center – Code Generation, Customizable GUI, Real-Time Tuning
    • Free Professional Development Environments
  • 12-KB ROM Library Includes CapTIvate Touch Libraries and Driver Libraries
  • Family Members (Also See Device Comparison)
    • MSP430FR2633: 15KB of Program FRAM + 512B of Information FRAM + 4KB of RAM
      up to 16 Self-Capacitive or 64 Mutual-Capacitive Sensors
    • MSP430FR2533: 15KB of Program FRAM + 512B of Information FRAM + 2KB of RAM
      up to 16 Self-Capacitive or 16 Mutual-Capacitive Sensors
    • MSP430FR2632: 8KB of Program FRAM + 512B of Information FRAM + 2KB of RAM
      up to 8 Self-Capacitive or 16 Mutual-Capacitive Sensors
    • MSP430FR2532: 8KB of Program FRAM + 512B of Information FRAM + 1KB of RAM
      up to 8 Self-Capacitive or 8 Mutual-Capacitive Sensors
  • Package Options
    • 32-Pin: VQFN (RHB)
    • 32-Pin: TSSOP (DA)
    • 24-Pin: VQFN (RGE)
    • 24-Pin: DSBGA (YQW)
  • For Complete Module Descriptions, See the MSP430FR4xx and MSP430FR2xx Family User's Guide
Minimum supply voltage is restricted by SVS levels (see V
Minimum supply voltage is restricted by SVS levels (see VSVSH- and VSVSH+ in PMM, SVS and BOR).

Applications

  • Electronic Smart Locks, Door Keypads, and Readers
  • Garage door Systems
  • Intrusion HMI Keypads and Control Panels
  • Motorized Window Blinds
  • Remote Controls
  • Personal Electronics
  • Wireless Speakers and Headsets
  • Handheld Video Game Controllers
  • A/V Receivers
  • White Goods
  • Small Appliances
  • Garden and Power Tools

Description

The MSP430FR263x and MSP430FR253x are ultra-low-power MSP430™ microcontrollers for capacitive touch sensing that feature CapTIvate touch technology for buttons, sliders, wheels, and proximity applications. MSP430 MCUs with CapTIvate technology provide the most integrated and autonomous capacitive-touch solution in the market with high reliability and noise immunity at the lowest power. TI's capacitive touch technology supports concurrent self-capacitance and mutual-capacitance electrodes on the same design for maximum flexibility. MSP430 MCUs with CapTIvate technology operate through thick glass, plastic enclosures, metal and wood with operation in harsh environments including wet, greasy and dirty environments.

TI capacitive touch sensing MSP430 MCUs are supported by an extensive hardware and software ecosystem with reference designs and code examples to get your design started quickly. Development kits include the MSP-CAPT-FR2633 CapTIvate technology development kit. TI also provides free software including the CapTIvate Design Center, where engineers can quickly develop applications with an easy-to-use GUI and MSP430Ware™ software and comprehensive documentation with the CapTIvate technology guide.

TI's MSP430 ultra-low-power (ULP) FRAM microcontroller platform combines uniquely embedded FRAM and a holistic ultra-low-power system architecture, allowing system designers to increase performance while lowering energy consumption. FRAM technology combines the low-energy fast writes, flexibility, and endurance of RAM with the nonvolatility of flash.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE(2)
MSP430FR2633IRHB VQFN (32)5 mm × 5 mm
MSP430FR2533IRHB VQFN (32)5 mm × 5 mm
MSP430FR2633IDA TSSOP (32)11 mm × 6.2 mm
MSP430FR2533IDA TSSOP (32)11 mm × 6.2 mm
MSP430FR2632IRGE VQFN (24)4 mm × 4 mm
MSP430FR2532IRGE VQFN (24)4 mm × 4 mm
MSP430FR2633IYQW DSBGA (24) 2.29 mm × 2.34 mm
MSP430FR2632IYQW DSBGA (24)2.29 mm × 2.34 mm
For the most current part, package, and ordering information, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 9.

CAUTION

System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical overstress or disturbing of data or code memory. See MSP430 System-Level ESD Considerations for more information.

Functional Block Diagram

Figure 1-1 shows the functional block diagram.

MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 SLAS942_Functional_Block_Diagram.gif Figure 1-1 Functional Block Diagram
  • The MCU has one main power pair of DVCC and DVSS that supplies digital and analog modules. Recommended bypass and decoupling capacitors are 4.7 µF to 10 µF and 0.1 µF, respectively, with ±5% accuracy.
  • VREG is the decoupling capacitor of the CapTIvate regulator. The recommended value for the required decoupling capacitor is 1 µF, with a maximum ESR of ≤200 mΩ.
  • P1 and P2 feature the pin interrupt function and can wake the MCU from all LPMs, including LPM3.5 and LPM4.
  • Each Timer_A3 has three capture/compare registers. Only CCR1 and CCR2 are externally connected. CCR0 registers can be used only for internal period timing and interrupt generation.
  • Each Timer_A2 has two capture/compare registers. Both registers can be used only for internal period timing and interrupt generation.
  • In LPM3 mode, the CapTIvate module can be functional while the rest of the peripherals are off.