SLAS734G April 2011  – April 2016 MSP430G2203 , MSP430G2233 , MSP430G2303 , MSP430G2333 , MSP430G2403 , MSP430G2433 , MSP430G2533

PRODUCTION DATA. 

  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagrams
    2. 4.2Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5 Typical Characteristics, Active Mode Supply Current (Into VCC)
    6. 5.6 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    7. 5.7 Typical Characteristics, Low-Power Mode Supply Currents
    8. 5.8 Thermal Resistance Characteristics
    9. 5.9 Schmitt-Trigger Inputs, Ports Px
    10. 5.10Leakage Current, Ports Px
    11. 5.11Outputs, Ports Px
    12. 5.12Output Frequency, Ports Px
    13. 5.13Typical Characteristics - Outputs
    14. 5.14Pin-Oscillator Frequency - Ports Px
    15. 5.15Typical Characteristics - Pin-Oscillator Frequency
    16. 5.16POR, BOR
    17. 5.17Main DCO Characteristics
    18. 5.18DCO Frequency
    19. 5.19Calibrated DCO Frequencies, Tolerance
    20. 5.20Wake-up Times From Lower-Power Modes (LPM3, LPM4)
    21. 5.21Typical Characteristics, DCO Clock Wake-up Time From LPM3 or LPM4
    22. 5.22Crystal Oscillator, XT1, Low-Frequency Mode
    23. 5.23Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    24. 5.24Timer_A
    25. 5.25USCI (UART Mode)
    26. 5.26USCI (SPI Master Mode)
    27. 5.27USCI (SPI Slave Mode)
    28. 5.28USCI (I2C Mode)
    29. 5.2910-Bit ADC, Power Supply and Input Range Conditions (MSP430G2x33 Only)
    30. 5.3010-Bit ADC, Built-In Voltage Reference (MSP430G2x33 Only)
    31. 5.3110-Bit ADC, External Reference (MSP430G2x33 Only)
    32. 5.3210-Bit ADC, Timing Parameters (MSP430G2x33 Only)
    33. 5.3310-Bit ADC, Linearity Parameters (MSP430G2x33 Only)
    34. 5.3410-Bit ADC, Temperature Sensor and Built-In VMID (MSP430G2x33 Only)
    35. 5.35Flash Memory
    36. 5.36RAM
    37. 5.37JTAG and Spy-Bi-Wire Interface
    38. 5.38JTAG Fuse
  6. 6Detailed Description
    1. 6.1 CPU
    2. 6.2 Instruction Set
    3. 6.3 Operating Modes
    4. 6.4 Interrupt Vector Addresses
    5. 6.5 Special Function Registers (SFRs)
    6. 6.6 Memory Organization
    7. 6.7 Bootloader (BSL)
    8. 6.8 Flash Memory
    9. 6.9 Peripherals
      1. 6.9.1Oscillator and System Clock
      2. 6.9.2Calibration Data Stored in Information Memory Segment A
      3. 6.9.3Brownout
      4. 6.9.4Digital I/O
      5. 6.9.5WDT+ Watchdog Timer
      6. 6.9.6Timer_A3 (TA0, TA1)
      7. 6.9.7Universal Serial Communications Interface (USCI)
      8. 6.9.8ADC10 (MSP430G2x33 Only)
      9. 6.9.9Peripheral File Map
    10. 6.10I/O Port Diagrams
      1. 6.10.1Port P1 Pin Diagram: P1.0 to P1.2, Input/Output With Schmitt Trigger
      2. 6.10.2Port P1 Pin Diagram: P1.3, Input/Output With Schmitt Trigger
      3. 6.10.3Port P1 Pin Diagram: P1.4, Input/Output With Schmitt Trigger
      4. 6.10.4Port P1 Pin Diagram: P1.5 to P1.7, Input/Output With Schmitt Trigger
      5. 6.10.5Port P2 Pin Diagram: P2.0 to P2.5, Input/Output With Schmitt Trigger
      6. 6.10.6Port P2 Pin Diagram: P2.6, Input/Output With Schmitt Trigger
      7. 6.10.7Port P2 Pin Diagram: P2.7, Input/Output With Schmitt Trigger
      8. 6.10.8Port P3 Pin Diagram: P3.0 to P3.7, Input/Output With Schmitt Trigger (RHB and PW28 Package Only)
  7. 7Device and Documentation Support
    1. 7.1Getting Started and Next Steps
    2. 7.2Device Nomenclature
    3. 7.3Tools and Software
    4. 7.4Documentation Support
    5. 7.5Related Links
    6. 7.6Community Resources
    7. 7.7Trademarks
    8. 7.8Electrostatic Discharge Caution
    9. 7.9Glossary
  8. 8Mechanical, Packaging, and Orderable Information

6 Detailed Description

6.1 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers (see Figure 6-1).

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 slas000-040.gif Figure 6-1 Integrated CPU Registers

6.2 Instruction Set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 6-1 lists examples of the three types of instruction formats. Table 6-2 lists the address modes.

Table 6-1 Instruction Word Formats

INSTRUCTION FORMATEXAMPLEOPERATION
Dual operands, source-destinationADD R4,R5R4 + R5 → R5
Single operands, destination onlyCALL R8PC → (TOS), R8 → PC
Relative jump, unconditional or conditionalJNEJump-on-equal bit = 0

Table 6-2 Address Mode Descriptions

ADDRESS MODES(1)DSYNTAXEXAMPLEOPERATION
RegisterMOV Rs,RdMOV R10,R11R10 → R11
IndexedMOV X(Rn),Y(Rm)MOV 2(R5),6(R6)M(2+R5) → M(6+R6)
Symbolic (PC relative)MOV EDE,TONIM(EDE) → M(TONI)
AbsoluteMOV &MEM,&TCDATM(MEM) → M(TCDAT)
IndirectMOV @Rn,Y(Rm)MOV @R10,Tab(R6)M(R10) → M(Tab+R6)
Indirect autoincrementMOV @Rn+,RmMOV @R10+,R11M(R10) → R11
R10 + 2 → R10
ImmediateMOV #X,TONIMOV #45,TONI#45 → M(TONI)
(1) S = source, D = destination

6.3 Operating Modes

These microcontrollers have one active mode and five software-selectable low-power modes of operation. An interrupt event can wake the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

Software can configure the following operating modes:

  • Active mode (AM)
    • All clocks are active
  • Low-power mode 0 (LPM0)
    • CPU is disabled
    • ACLK and SMCLK remain active, MCLK is disabled
  • Low-power mode 1 (LPM1)
    • CPU is disabled
    • ACLK and SMCLK remain active, MCLK is disabled
    • DC generator of the DCO is disabled if DCO not used in active mode
  • Low-power mode 2 (LPM2)
    • CPU is disabled
    • MCLK and SMCLK are disabled
    • DC generator of the DCO remains enabled
    • ACLK remains active
  • Low-power mode 3 (LPM3)
    • CPU is disabled
    • MCLK and SMCLK are disabled
    • DC generator of the DCO is disabled
    • ACLK remains active
  • Low-power mode 4 (LPM4)
    • CPU is disabled
    • ACLK is disabled
    • MCLK and SMCLK are disabled
    • DC generator of the DCO is disabled
    • Crystal oscillator is stopped

6.4 Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are in the address range 0FFFFh to 0FFC0h (see Table 6-3). The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (at address 0FFFEh) contains 0FFFFh (for example, if the flash is not programmed), the CPU goes into LPM4 immediately after power-up.

Table 6-3 Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCEINTERRUPT FLAGSYSTEM INTERRUPTWORD ADDRESSPRIORITY
Power up
External reset
Watchdog Timer+
Flash key violation
PC out of range(1)
PORIFG
RSTIFG
WDTIFG
KEYV(2)
Reset0FFFEh31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG(2)
(non)-maskable(6)
(non)-maskable
(non)-maskable
0FFFCh30
Timer1_A3TACCR0 CCIFG(3)maskable0FFFAh29
Timer1_A3TACCR2 TACCR1 CCIFG, TAIFG(2)(3)maskable0FFF8h28
0FFF6h27
Watchdog Timer+WDTIFGmaskable0FFF4h26
Timer0_A3TACCR0 CCIFG(3)maskable0FFF2h25
Timer0_A3TACCR2 TACCR1 CCIFG, TAIFG (4)(3)maskable0FFF0h24
USCI_A0, USCI_B0 receive
USCI_B0 I2C status
UCA0RXIFG, UCB0RXIFG(2)(4)maskable0FFEEh23
USCI_A0, USCI_B0 transmit
USCI_B0 I2C receive or transmit
UCA0TXIFG, UCB0TXIFG(2)(5)maskable0FFECh22
ADC10
(MSP430G2x33 only)
ADC10IFG(3)maskable0FFEAh21
0FFE8h20
I/O Port P2 (up to eight flags)P2IFG.0 to P2IFG.7(2)(3)maskable0FFE6h19
I/O Port P1 (up to eight flags)P1IFG.0 to P1IFG.7(2)(3)maskable0FFE4h18
0FFE2h17
0FFE0h16
See (7)0FFDEh15
See (8)0FFDEh to 0FFC0h14 to 0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from within unused address ranges.
(2) Multiple source flags
(3) Interrupt flags are in the module.
(4) In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
(5) In UART or SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
(6) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(7) This location is used as bootloader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0h) disables the erasure of the flash if an invalid password is supplied.
(8) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if necessary.

6.5 Special Function Registers (SFRs)

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

Legend
rwBit can be read and written.
rw-0, rw-1Bit can be read and written. It is reset or set by PUC.
rw-(0), rw-(1)Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Figure 6-2 Interrupt Enable Register 1 (Address = 00h)
76543210
ACCVIENMIIEOFIEWDTIE
rw-0rw-0rw-0rw-0

Table 6-4 Interrupt Enable Register 1 Description

BitFieldTypeResetDescription
5ACCVIERW0hFlash access violation interrupt enable
4NMIIERW0h(Non)maskable interrupt enable
1OFIERW0hOscillator fault interrupt enable
0WDTIERW0hWatchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode.
Figure 6-3 Interrupt Enable Register 2 (Address = 01h)
76543210
 UCB0TXIEUCB0RXIEUCA0TXIEUCA0RXIE
 rw-0rw-0rw-0rw-0

Table 6-5 Interrupt Enable Register 2 Description

BitFieldTypeResetDescription
3UCB0TXIERW0hUSCI_B0 transmit interrupt enable
2UCB0RXIERW0hUSCI_B0 receive interrupt enable
1UCA0TXIERW0hUSCI_A0 transmit interrupt enable
0UCA0RXIERW0hUSCI_A0 receive interrupt enable
Figure 6-4 Interrupt Flag Register 1 (Address = 02h)
76543210
NMIIFGRSTIFGPORIFGOFIFGWDTIFG
rw-0rw-(0)rw-(1)rw-1rw-(0)

Table 6-6 Interrupt Flag Register 1 Description

BitFieldTypeResetDescription
4NMIIFGRW0hSet by the RST/NMI pin
3RSTIFGRW0hExternal reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
2PORIFGRW1hPower-On Reset interrupt flag. Set on VCC power-up.
1OFIFGRW1hFlag set on oscillator fault.
0WDTIFGRW0hSet on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
Figure 6-5 Interrupt Flag Register 2 (Address = 03h)
76543210
 UCB0TXIFGUCB0RXIFGUCA0TXIFGUCA0RXIFG
 rw-1rw-0rw-1rw-0

Table 6-7 Interrupt Flag Register 2 Description

BitFieldTypeResetDescription
3UCB0TXIFGRW0hUSCI_B0 transmit interrupt flag
2UCB0RXIFGRW1hUSCI_B0 receive interrupt flag
1UCA0TXIFGRW1hUSCI_A0 transmit interrupt flag
0UCA0RXIFGRW0hUSCI_A0 receive interrupt flag

6.6 Memory Organization

Table 6-8 summarizes the memory map.

Table 6-8 Memory Organization

MSP430G2233
MSP430G2203
MSP430G2333
MSP430G2303
MSP430G2433
MSP430G2403
MSP430G2533
MemorySize2KB4KB8KB16KB
Main: interrupt vectorFlashFFFFh to FFC0hFFFFh to FFC0hFFFFh to FFC0hFFFFh to FFC0h
Main: code memoryFlashFFFFh to F800hFFFFh to F000hFFFFh to E000hFFFFh to C000h
Information memorySize256 byte256 byte256 byte256 byte
Flash010FFh to 01000h010FFh to 01000h010FFh to 01000h010FFh to 01000h
RAMSize256 byte256 byte512 byte512 byte
02FFh to 0200h02FFh to 0200h03FFh to 0200h03FFh to 0200h
Peripherals16-bit01FFh to 0100h01FFh to 0100h01FFh to 0100h01FFh to 0100h
8-bit0FFh to 010h0FFh to 010h0FFh to 010h0FFh to 010h
8-bit SFR0Fh to 00h0Fh to 00h0Fh to 00h0Fh to 00h

6.7 Bootloader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory through the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the MSP430 Programming With the Bootloader User's Guide (SLAU319). Table 6-9 lists the BSL function pins.

Table 6-9 BSL Function Pins

BSL FUNCTION20-PIN PW PACKAGE
20-PIN N PACKAGE
28-PIN PW PACKAGE32-PIN RHB PACKAGE
Data transmit3 - P1.13 - P1.11 - P1.1
Data receive7 - P1.57 - P1.55 - P1.5

6.8 Flash Memory

The flash memory can be programmed through the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

  • Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size.
  • Segments 0 to n may be erased in one step, or each segment may be individually erased.
  • Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also called information memory.
  • Segment A contains calibration data. After reset segment A is protected against programming and erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required.

6.9 Peripherals

Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be managed using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).

6.9.1 Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turnon clock source and stabilizes in less than 1 µs. The basic clock module provides the following clock signals:

  • Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
  • Main clock (MCLK), the system clock used by the CPU.
  • Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules.

The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.

6.9.2 Calibration Data Stored in Information Memory Segment A

Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure (see Table 6-10 and Table 6-11).

Table 6-10 Tags Used by the ADC Calibration Tags

NAMEADDRESSVALUEDESCRIPTION
TAG_DCO_300x10F60x01DCO frequency calibration at VCC = 3 V and TA = 30°C
TAG_ADC10_10x10DA0x10ADC10_1 calibration tag
TAG_EMPTY0xFEIdentifier for empty memory areas

Table 6-11 Labels Used by the ADC Calibration Tags

LABELADDRESS OFFSETSIZECONDITION AT CALIBRATION
CAL_ADC_25T850x0010wordINCHx = 1010b, REF2_5 = 1, TA = 85°C
CAL_ADC_25T300x000EwordINCHx = 1010b, REF2_5 = 1, TA = 30°C
CAL_ADC_25VREF_FACTOR0x000CwordREF2_5 = 1, TA = 30°C, IVREF+ = 1 mA
CAL_ADC_15T850x000AwordINCHx = 1010b, REF2_5 = 0, TA = 85°C
CAL_ADC_15T300x0008wordINCHx = 1010b, REF2_5 = 0, TA = 30°C
CAL_ADC_15VREF_FACTOR0x0006wordREF2_5 = 0, TA = 30°C, IVREF+ = 0.5 mA
CAL_ADC_OFFSET0x0004wordExternal VREF = 1.5 V, fADC10CLK = 5 MHz
CAL_ADC_GAIN_FACTOR0x0002wordExternal VREF = 1.5 V, fADC10CLK = 5 MHz
CAL_BC1_1MHZ0x0009byte –
CAL_DCO_1MHZ0x0008byte –
CAL_BC1_8MHZ0x0007byte –
CAL_DCO_8MHZ0x0006byte –
CAL_BC1_12MHZ0x0005byte –
CAL_DCO_12MHZ0x0004byte –
CAL_BC1_16MHZ0x0003byte –
CAL_DCO_16MHZ0x0002byte –

6.9.3 Brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off.

6.9.4 Digital I/O

Up to three 8-bit I/O ports are implemented:

  • All individual I/O bits are independently programmable.
  • Any combination of input, output, and interrupt condition (port P1 and port P2 only) is possible.
  • Edge-selectable interrupt input capability for all bits of port P1 and port P2 (if available).
  • Read/write access to port-control registers is supported by all instructions.
  • Each I/O has an individually programmable pullup or pulldown resistor.
  • Each I/O has an individually programmable pin oscillator enable bit to enable low-cost capacitive touch detection.

6.9.5 WDT+ Watchdog Timer

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.

6.9.6 Timer_A3 (TA0, TA1)

Timer0_A3 and Timer1_A3 are 16-bit timers/counters with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-12 and Table 6-13). Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 6-12 Timer0_A3 Signal Connections

INPUT PIN NUMBERDEVICE INPUT SIGNALMODULE INPUT NAMEMODULE BLOCKMODULE OUTPUT SIGNALOUTPUT PIN NUMBER
PW20, N20PW28RHB32PW20, N20PW28RHB32
P1.0-2P1.0-2P1.0-31TACLKTACLKTimerNA
ACLKACLK
SMCLKSMCLK
PinOscPinOscPinOscTACLKINCLK
P1.1-3P1.1-3P1.1-1TA0.0CCI0ACCR0TA0P1.1-3P1.1-3P1.1-1
ACLKCCI0BP1.5-7P1.5-7P1.5-5
VSSGNDP3.4-15P3.4-14
VCCVCC
P1.2-4P1.2-4P1.2-2TA0.1CCI1ACCR1TA1P1.2-4P1.2-4P1.2-2
CAOUTCCI1BP1.6-14P1.6-22P1.6-21
VSSGNDP2.6-19P2.6-27P2.6-26
VCCVCCP3.5-19P3.5-18
P3.0-9P3.0-7TA0.2CCI2ACCR2TA2P3.0-9P3.0-7
PinOscPinOscPinOscTA0.2CCI2BP3.6-20P3.6-19
VSSGND
VCCVCC

Table 6-13 Timer1_A3 Signal Connections

INPUT PIN NUMBERDEVICE INPUT SIGNALMODULE INPUT NAMEMODULE BLOCKMODULE OUTPUT SIGNALOUTPUT PIN NUMBER
PW20, N20PW28RHB32PW20, N20PW28RHB32
P3.7-21P3.7-20TACLKTACLKTimerNA
ACLKACLK
SMCLKSMCLK
P3.7-21P3.7-20TACLKINCLK
P2.0-8P2.0-10P2.0-9TA1.0CCI0ACCR0TA0P2.0-8P2.0-10P2.0-9
P2.3-11P2.3-16P2.3-12TA1.0CCI0BP2.3-11P2.3-16P2.3-15
VSSGNDP3.1-8P3.1-6
VCCVCC
P2.1-9P2.1-11P2.1-10TA1.1CCI1ACCR1TA1P2.1-9P2.1-11P2.1-10
P2.2-10P2.2-12P2.2-11TA1.1CCI1BP2.2-10P2.2-12P2.2-11
VSSGNDP3.2-13P3.2-12
VCCVCC
P2.4-12P2.4-17P2.4-16TA1.2CCI2ACCR2TA2P2.4-12P2.4-17P2.4-16
P2.5-13P2.5-18P2.5-17TA1.2CCI2BP2.5-13P2.5-18P2.5-17
VSSGNDP3.3-14P3.3-13
VCCVCC

6.9.7 Universal Serial Communications Interface (USCI)

The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baud rate detection (LIN), and IrDA. Not all packages support the USCI functionality.

USCI_A0 provides support for SPI (3-pin or 4-pin), UART, enhanced UART, and IrDA.

USCI_B0 provides support for SPI (3-pin or 4-pin) and I2C.

6.9.8 ADC10 (MSP430G2x33 Only)

The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and data transfer controller (DTC) for automatic conversion result handling, allowing ADC samples to be converted and stored without any CPU intervention.

6.9.9 Peripheral File Map

Table 6-14 lists the registers that support word access. Table 6-15 that support byte access.

Table 6-14 Peripherals With Word Access

MODULEREGISTER DESCRIPTIONACRONYMOFFSET
ADC10 (MSP430G2x33 only)ADC data transfer start addressADC10SA1BCh
ADC memoryADC10MEM1B4h
ADC control register 1ADC10CTL11B2h
ADC control register 0ADC10CTL01B0h
Timer1_A3Capture/compare registerTA1CCR20196h
Capture/compare registerTA1CCR10194h
Capture/compare registerTA1CCR00192h
Timer_A registerTA1R0190h
Capture/compare controlTA1CCTL20186h
Capture/compare controlTA1CCTL10184h
Capture/compare controlTA1CCTL00182h
Timer_A controlTA1CTL0180h
Timer_A interrupt vectorTA1IV011Eh
Timer0_A3Capture/compare registerTA0CCR20176h
Capture/compare registerTA0CCR10174h
Capture/compare registerTA0CCR00172h
Timer_A registerTA0R0170h
Capture/compare controlTA0CCTL20166h
Capture/compare controlTA0CCTL10164h
Capture/compare controlTA0CCTL00162h
Timer_A controlTA0CTL0160h
Timer_A interrupt vectorTA0IV012Eh
Flash MemoryFlash control 3FCTL3012Ch
Flash control 2FCTL2012Ah
Flash control 1FCTL10128h
Watchdog Timer+Watchdog timer controlWDTCTL0120h

Table 6-15 Peripherals With Byte Access

MODULEREGISTER DESCRIPTIONACRONYMOFFSET
USCI_B0USCI_B0 transmit bufferUCB0TXBUF06Fh
USCI_B0 receive bufferUCB0RXBUF06Eh
USCI_B0 statusUCB0STAT06Dh
USCI B0 I2C Interrupt enableUCB0CIE06Ch
USCI_B0 bit rate control 1UCB0BR106Bh
USCI_B0 bit rate control 0UCB0BR006Ah
USCI_B0 control 1UCB0CTL1069h
USCI_B0 control 0UCB0CTL0068h
USCI_B0 I2C slave addressUCB0SA011Ah
USCI_B0 I2C own addressUCB0OA0118h
USCI_A0USCI_A0 transmit bufferUCA0TXBUF067h
USCI_A0 receive bufferUCA0RXBUF066h
USCI_A0 statusUCA0STAT065h
USCI_A0 modulation controlUCA0MCTL064h
USCI_A0 baud rate control 1UCA0BR1063h
USCI_A0 baud rate control 0UCA0BR0062h
USCI_A0 control 1UCA0CTL1061h
USCI_A0 control 0UCA0CTL0060h
USCI_A0 IrDA receive controlUCA0IRRCTL05Fh
USCI_A0 IrDA transmit controlUCA0IRTCTL05Eh
USCI_A0 auto baud rate controlUCA0ABCTL05Dh
ADC10 (MSP430G2x33 only)ADC analog enable 0ADC10AE004Ah
ADC analog enable 1ADC10AE104Bh
ADC data transfer control register 1ADC10DTC1049h
ADC data transfer control register 0ADC10DTC0048h
Basic Clock System+Basic clock system control 3BCSCTL3053h
Basic clock system control 2BCSCTL2058h
Basic clock system control 1BCSCTL1057h
DCO clock frequency controlDCOCTL056h
Port P3
(28-pin PW and 32-pin RHB only)
Port P3 selection 2. pinP3SEL2043h
Port P3 resistor enableP3REN010h
Port P3 selectionP3SEL01Bh
Port P3 directionP3DIR01Ah
Port P3 outputP3OUT019h
Port P3 inputP3IN018h
Port P2Port P2 selection 2P2SEL2042h
Port P2 resistor enableP2REN02Fh
Port P2 selectionP2SEL02Eh
Port P2 interrupt enableP2IE02Dh
Port P2 interrupt edge selectP2IES02Ch
Port P2 interrupt flagP2IFG02Bh
Port P2 directionP2DIR02Ah
Port P2 outputP2OUT029h
Port P2 inputP2IN028h
Port P1Port P1 selection 2P1SEL2041h
Port P1 resistor enableP1REN027h
Port P1 selectionP1SEL026h
Port P1 interrupt enableP1IE025h
Port P1 interrupt edge selectP1IES024h
Port P1 interrupt flagP1IFG023h
Port P1 directionP1DIR022h
Port P1 outputP1OUT021h
Port P1 inputP1IN020h
Special FunctionSFR interrupt flag 2IFG2003h
SFR interrupt flag 1IFG1002h
SFR interrupt enable 2IE2001h
SFR interrupt enable 1IE1000h

6.10 I/O Port Diagrams

6.10.1 Port P1 Pin Diagram: P1.0 to P1.2, Input/Output With Schmitt Trigger

Figure 6-6 shows the port diagram. Table 6-16 summarizes the selection of the pin functions.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 p1_012_las734.gif Figure 6-6 Port P1 (P1.0 to P1.2) Diagram

Table 6-16 Port P1 (P1.0 to P1.2) Pin Functions

PIN NAME (P1.x)xFUNCTIONCONTROL BITS OR SIGNALS(1)
P1DIR.xP1SEL.xP1SEL2.xADC10AE.x
(INCH.y = 1)(2)
P1.0/0P1.x (I/O)I: 0; O: 1000
TA0CLK/TA0.TACLK0100
ACLK/ACLK1100
A0(2)/A0XXX1 (y = 0)
Pin OscCapacitive sensingX010
P1.1/1P1.x (I/O)I: 0; O: 1000
TA0.0/TA0.01100
TA0.CCI0A0100
UCA0RXD/UCA0RXDfrom USCI110
UCA0SOMI/UCA0SOMIfrom USCI110
A1(2)/A1XXX1 (y = 1)
Pin OscCapacitive sensingX010
P1.2/2P1.x (I/O)I: 0; O: 1000
TA0.1/TA0.11100
TA0.CCI1A0100
UCA0TXD/UCA0TXDfrom USCI110
UCA0SIMO/UCA0SIMOfrom USCI110
A2(2)/A2XXX1 (y = 2)
Pin OscCapacitive sensingX010
(1) X = don't care
(2) MSP430G2x33 devices only

6.10.2 Port P1 Pin Diagram: P1.3, Input/Output With Schmitt Trigger

Figure 6-7 shows the port diagram. Table 6-17 summarizes the selection of the pin functions.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 p1_3_las734.gif Figure 6-7 Port P1 (P1.3) Diagram

Table 6-17 Port P1 (P1.3) Pin Functions

PIN NAME (P1.x)xFUNCTIONCONTROL BITS OR SIGNALS(1)
P1DIR.xP1SEL.xP1SEL2.xADC10AE.x
(INCH.y = 1)(2)
P1.3/3P1.x (I/O)I: 0; O: 1000
ADC10CLK(2)/ADC10CLK1100
A3(2)/A3XXX1 (y = 3)
VREF-(2)/VREF-XXX1
VEREF-(2)/VEREF-XXX1
Pin OscCapacitive sensingX010

6.10.3 Port P1 Pin Diagram: P1.4, Input/Output With Schmitt Trigger

Figure 6-8 shows the port diagram. Table 6-18 summarizes the selection of the pin functions.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 p1_4_las734.gif Figure 6-8 Port P1 (P1.4) Diagram

Table 6-18 Port P1 (P1.4) Pin Functions

PIN NAME (P1.x)xFUNCTIONCONTROL BITS OR SIGNALS(1)
P1DIR.xP1SEL.xP1SEL2.xADC10AE.x
(INCH.y = 1)(2)
JTAG Mode
P1.4/4P1.x (I/O)I: 0; O: 10000
SMCLK/SMCLK11000
UCB0STE/UCB0STE(1)(2)from USCI1100
UCA0CLK/UCA0CLK(1)(2)from USCI1100
VREF+(2)/VREF+XXX10
VEREF+(2)/VEREF+XXX10
A4(2)/A4XXX1 (y = 4)0
TCK/TCKXXX01
Pin OscCapacitive sensingX0100
(1) The pin direction is controlled by the USCI module.
(2) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to 3-wire SPI mode if 4-wire SPI mode is selected.

6.10.4 Port P1 Pin Diagram: P1.5 to P1.7, Input/Output With Schmitt Trigger

Figure 6-9 shows the port diagram. Table 6-19 summarizes the selection of the pin functions.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 p1_567_las734.gif Figure 6-9 Port P1 (P1.5 to P1.7) Diagram

Table 6-19 Port P1 (P1.5 to P1.7) Pin Functions

PIN NAME (P1.x)xFUNCTIONCONTROL BITS OR SIGNALS(1)
P1DIR.xP1SEL.xP1SEL2.xADC10AE.x
(INCH.y = 1)(2)
JTAG Mode
P1.5/5P1.x (I/O)I: 0; O: 10000
TA0.0/TA0.011000
UCB0CLK/UCB0CLK(1)(2)from USCI1100
UCA0STE/UCA0STE(1)(2)from USCI1100
A5(2)/A5XXX1 (y = 5)0
TMSTMSXXX01
Pin OscCapacitive sensingX0100
P1.6/6P1.x (I/O)I: 0; O: 10000
TA0.1/TA0.111000
UCB0SOMI/UCB0SOMIfrom USCI1100
UCB0SCL/UCB0SCLfrom USCI1100
A6(2)/A6XXX1 (y = 6)0
TDI/TCLK/TDI/TCLKXXX01
Pin OscCapacitive sensingX0100
P1.7/7P1.x (I/O)I: 0; O: 10000
UCB0SIMO/UCB0SIMOfrom USCI1100
UCB0SDA/UCB0SDAfrom USCI1100
A7(2)/A7XXX1 (y = 7)0
TDO/TDI/TDO/TDIXXX01
Pin OscCapacitive sensingX0100
(1) The pin direction is controlled by the USCI module.
(2) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to 3-wire SPI mode if 4-wire SPI mode is selected.

6.10.5 Port P2 Pin Diagram: P2.0 to P2.5, Input/Output With Schmitt Trigger

Figure 6-10 shows the port diagram. Table 6-20 summarizes the selection of the pin functions.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 p2_012345_las734.gif Figure 6-10 Port P2 (P2.0 to P2.5) Diagram

Table 6-20 Port P2 (P2.0 to P2.5) Pin Functions

PIN NAME (P2.x)xFUNCTIONCONTROL BITS OR SIGNALS(1)
P2DIR.xP2SEL.xP2SEL2.x
P2.0/0P2.x (I/O)I: 0; O: 100
TA1.0/Timer1_A3.CCI0A010
Timer1_A3.TA0110
Pin OscCapacitive sensingX01
P2.1/1P2.x (I/O)I: 0; O: 100
TA1.1/Timer1_A3.CCI1A010
Timer1_A3.TA1110
Pin OscCapacitive sensingX01
P2.2/2P2.x (I/O)I: 0; O: 100
TA1.1/Timer1_A3.CCI1B010
Timer1_A3.TA1110
Pin OscCapacitive sensingX01
P2.3/3P2.x (I/O)I: 0; O: 100
TA1.0/Timer1_A3.CCI0B010
Timer1_A3.TA0110
Pin OscCapacitive sensingX01
P2.4/4P2.x (I/O)I: 0; O: 100
TA1.2/Timer1_A3.CCI2A010
Timer1_A3.TA2110
Pin OscCapacitive sensingX01
P2.5/5P2.x (I/O)I: 0; O: 100
TA1.2/Timer1_A3.CCI2B010
Timer1_A3.TA2110
Pin OscCapacitive sensingX01

6.10.6 Port P2 Pin Diagram: P2.6, Input/Output With Schmitt Trigger

Figure 6-11 shows the port diagram. Table 6-21 summarizes the selection of the pin functions.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 p2_6_las734.gif Figure 6-11 Port P2 (P2.6) Diagram

Table 6-21 Port P2 (P2.6) Pin Functions

PIN NAME (P2.x)xFUNCTIONCONTROL BITS OR SIGNALS(1)
P2DIR.xP2SEL.6
P2SEL.7
P2SEL2.6
P2SEL2.7
XIN6XIN01
1
0
0
P2.6P2.x (I/O)I: 0; O: 10
X
0
0
TA0.1Timer0_A3.TA111
0
0
0
Pin OscCapacitive sensingX0
X
1
X

6.10.7 Port P2 Pin Diagram: P2.7, Input/Output With Schmitt Trigger

Figure 6-12 shows the port diagram. Table 6-22 summarizes the selection of the pin functions.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 p2_7_las734.gif Figure 6-12 Port P2 (P2.7) Diagram

Table 6-22 Port P2 (P2.7) Pin Functions

PIN NAME (P2.x)xFUNCTIONCONTROL BITS OR SIGNALS(1)
P2DIR.xP2SEL.6
P2SEL.7
P2SEL2.6
P2SEL2.7
XOUT/7XOUT11
1
0
0
P2.7/P2.x (I/O)I: 0; O: 10
X
0
0
Pin OscCapacitive sensingX0
X
1
X

6.10.8 Port P3 Pin Diagram: P3.0 to P3.7, Input/Output With Schmitt Trigger (RHB and PW28 Package Only)

Figure 6-13 shows the port diagram. Table 6-23 summarizes the selection of the pin functions.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 p3_01234567_las734.gif Figure 6-13 Port P3 (P3.0 to P3.7) Diagram (RHB and PW28 Package Only)

Table 6-23 Port P3 (P3.0 to P3.7) Pin Functions (RHB and PW28 Package Only)

PIN NAME (P3.x)xFUNCTIONCONTROL BITS OR SIGNALS(1)
P3DIR.xP3SEL.xP3SEL2.x
P3.0/0P3.x (I/O)I: 0; O: 100
TA0.2/Timer0_A3.CCI2A010
Timer0_A3.TA2110
Pin OscCapacitive sensingX01
P3.1/1P3.x (I/O)I: 0; O: 100
TA1.0/Timer1_A3.TA0110
Pin OscCapacitive sensingX01
P3.2/2P3.x (I/O)I: 0; O: 100
TA1.1/Timer1_A3.TA1110
Pin OscCapacitive sensingX01
P3.3/3P3.x (I/O)I: 0; O: 100
TA1.2/Timer1_A3.TA2110
Pin OscCapacitive sensingX01
P3.4/4P3.x (I/O)I: 0; O: 100
TA0.0/Timer0_A3.TA0110
Pin OscCapacitive sensingX01
P3.5/5P3.x (I/O)I: 0; O: 100
TA0.1/Timer0_A3.TA1110
Pin OscCapacitive sensingX01
P3.6/6P3.x (I/O)I: 0; O: 100
TA0.2/Timer0_A3.TA2110
Pin OscCapacitive sensingX01
P3.7/7P3.x (I/O)I: 0; O: 100
TA1CLK/Timer1_A3.TACLK010
Pin OscCapacitive sensingX01