SLAS734G April 2011  – April 2016 MSP430G2203 , MSP430G2233 , MSP430G2303 , MSP430G2333 , MSP430G2403 , MSP430G2433 , MSP430G2533

PRODUCTION DATA. 

  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagrams
    2. 4.2Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5 Typical Characteristics, Active Mode Supply Current (Into VCC)
    6. 5.6 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    7. 5.7 Typical Characteristics, Low-Power Mode Supply Currents
    8. 5.8 Thermal Resistance Characteristics
    9. 5.9 Schmitt-Trigger Inputs, Ports Px
    10. 5.10Leakage Current, Ports Px
    11. 5.11Outputs, Ports Px
    12. 5.12Output Frequency, Ports Px
    13. 5.13Typical Characteristics - Outputs
    14. 5.14Pin-Oscillator Frequency - Ports Px
    15. 5.15Typical Characteristics - Pin-Oscillator Frequency
    16. 5.16POR, BOR
    17. 5.17Main DCO Characteristics
    18. 5.18DCO Frequency
    19. 5.19Calibrated DCO Frequencies, Tolerance
    20. 5.20Wake-up Times From Lower-Power Modes (LPM3, LPM4)
    21. 5.21Typical Characteristics, DCO Clock Wake-up Time From LPM3 or LPM4
    22. 5.22Crystal Oscillator, XT1, Low-Frequency Mode
    23. 5.23Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    24. 5.24Timer_A
    25. 5.25USCI (UART Mode)
    26. 5.26USCI (SPI Master Mode)
    27. 5.27USCI (SPI Slave Mode)
    28. 5.28USCI (I2C Mode)
    29. 5.2910-Bit ADC, Power Supply and Input Range Conditions (MSP430G2x33 Only)
    30. 5.3010-Bit ADC, Built-In Voltage Reference (MSP430G2x33 Only)
    31. 5.3110-Bit ADC, External Reference (MSP430G2x33 Only)
    32. 5.3210-Bit ADC, Timing Parameters (MSP430G2x33 Only)
    33. 5.3310-Bit ADC, Linearity Parameters (MSP430G2x33 Only)
    34. 5.3410-Bit ADC, Temperature Sensor and Built-In VMID (MSP430G2x33 Only)
    35. 5.35Flash Memory
    36. 5.36RAM
    37. 5.37JTAG and Spy-Bi-Wire Interface
    38. 5.38JTAG Fuse
  6. 6Detailed Description
    1. 6.1 CPU
    2. 6.2 Instruction Set
    3. 6.3 Operating Modes
    4. 6.4 Interrupt Vector Addresses
    5. 6.5 Special Function Registers (SFRs)
    6. 6.6 Memory Organization
    7. 6.7 Bootloader (BSL)
    8. 6.8 Flash Memory
    9. 6.9 Peripherals
      1. 6.9.1Oscillator and System Clock
      2. 6.9.2Calibration Data Stored in Information Memory Segment A
      3. 6.9.3Brownout
      4. 6.9.4Digital I/O
      5. 6.9.5WDT+ Watchdog Timer
      6. 6.9.6Timer_A3 (TA0, TA1)
      7. 6.9.7Universal Serial Communications Interface (USCI)
      8. 6.9.8ADC10 (MSP430G2x33 Only)
      9. 6.9.9Peripheral File Map
    10. 6.10I/O Port Diagrams
      1. 6.10.1Port P1 Pin Diagram: P1.0 to P1.2, Input/Output With Schmitt Trigger
      2. 6.10.2Port P1 Pin Diagram: P1.3, Input/Output With Schmitt Trigger
      3. 6.10.3Port P1 Pin Diagram: P1.4, Input/Output With Schmitt Trigger
      4. 6.10.4Port P1 Pin Diagram: P1.5 to P1.7, Input/Output With Schmitt Trigger
      5. 6.10.5Port P2 Pin Diagram: P2.0 to P2.5, Input/Output With Schmitt Trigger
      6. 6.10.6Port P2 Pin Diagram: P2.6, Input/Output With Schmitt Trigger
      7. 6.10.7Port P2 Pin Diagram: P2.7, Input/Output With Schmitt Trigger
      8. 6.10.8Port P3 Pin Diagram: P3.0 to P3.7, Input/Output With Schmitt Trigger (RHB and PW28 Package Only)
  7. 7Device and Documentation Support
    1. 7.1Getting Started and Next Steps
    2. 7.2Device Nomenclature
    3. 7.3Tools and Software
    4. 7.4Documentation Support
    5. 7.5Related Links
    6. 7.6Community Resources
    7. 7.7Trademarks
    8. 7.8Electrostatic Discharge Caution
    9. 7.9Glossary
  8. 8Mechanical, Packaging, and Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MINMAXUNIT
Voltage applied at VCC to VSS –0.34.1V
Voltage applied to any pin(2)–0.3VCC + 0.3V
Diode current at any device pin±2mA
Storage temperature, Tstg(3)Unprogrammed device–55150°C
Programmed device–55150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2 ESD Ratings

VALUEUNIT
V(ESD) Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±1000V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance.

5.3 Recommended Operating Conditions

Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MINNOMMAXUNIT
VCCSupply voltageDuring program execution1.83.6V
During flash programming or erase2.23.6
VSSSupply voltage0V
TAOperating free-air temperature–4085°C
fSYSTEM Processor frequency (maximum MCLK frequency using the USART module)(1)(2)VCC = 1.8 V,
Duty cycle = 50% ±10%
DC6MHz
VCC = 2.7 V,
Duty cycle = 50% ±10%
DC12
VCC = 3.3 V,
Duty cycle = 50% ±10%
DC16
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phases of MCLK must not exceed the pulse duration of the specified maximum frequency.
(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 safe_op_area_las694.gif
A.

NOTE:

Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.
Figure 5-1 Safe Operating Area

5.4 Active Mode Supply Current Into VCC Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
IAM,1MHzActive mode (AM) current at 1 MHzfDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 0 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
2.2 V230µA
3 V330420
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF.

5.5 Typical Characteristics, Active Mode Supply Current (Into VCC)

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_iam_vcc_las694.gif Figure 5-2 Active Mode Current vs VCC, TA = 25°C
MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_iam_fdco_las694.gif Figure 5-3 Active Mode Current vs DCO Frequency

5.6 Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETERTEST CONDITIONSTAVCCMINTYPMAXUNIT
ILPM0,1MHzLow-power mode 0 (LPM0) current(3)fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0
25°C2.2 V56µA
ILPM2Low-power mode 2 (LPM2) current(4)fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
25°C2.2 V22µA
ILPM3,LFXT1Low-power mode 3 (LPM3) current(4)fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25°C2.2 V0.71.5µA
ILPM3,VLOLow-power mode 3 current, (LPM3)(4)fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25°C2.2 V0.50.7µA
ILPM4Low-power mode 4 (LPM4) current(5)fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
25°C2.2 V0.10.5µA
85°C0.81.7
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF.
(3) Current for brownout and WDT clocked by SMCLK included.
(4) Current for brownout and WDT clocked by ACLK included.
(5) Current for brownout included.

5.7 Typical Characteristics, Low-Power Mode Supply Currents

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_ilpm3_ta_las694.gif Figure 5-4 LPM3 Current vs Temperature
MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_ilpm4_ta_las694.gif Figure 5-5 LPM4 Current vs Temperature

5.8 Thermal Resistance Characteristics

PARAMETERVALUE (4) UNIT
JA Junction-to-ambient thermal resistance, still air (1) VQFN (RHB-32)32.1°C/W
TSSOP (PW-28)72.2
TSSOP (PW-20)86.5
PDIP (N-20)49.3
JC(TOP) Junction-to-case (top) thermal resistance (2) VQFN (RHB-32)22.3°C/W
TSSOP (PW-28)18.3
TSSOP (PW-20)20.8
PDIP (N-20)41
JC(BOTTOM) Junction-to-case (bottom) thermal resistance VQFN (RHB-32)1.4°C/W
TSSOP (PW-28)N/A
TSSOP (PW-20)N/A
PDIP (N-20)N/A
θJB Junction-to-board thermal resistance (3) VQFN (RHB-32)6.1°C/W
TSSOP (PW-28)30.4
TSSOP (PW-20)39
PDIP (N-20)30.2
ΨJT Junction-to-package-top characterization parameterVQFN (RHB-32)0.3°C/W
TSSOP (PW-28)0.7
TSSOP (PW-20)0.8
PDIP (N-20)18.1
ΨJB Junction-to-board characterization parameterVQFN (RHB-32)6.1°C/W
TSSOP (PW-28)29.9
TSSOP (PW-20)38.1
PDIP (N-20)30.1
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(4) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (RθJC) value, which is based on a JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC standards:
  • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
  • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
  • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
  • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

5.9 Schmitt-Trigger Inputs, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
VIT+Positive-going input threshold voltage0.45 VCC0.75 VCCV
3 V1.352.25
VIT–Negative-going input threshold voltage0.25 VCC0.55 VCCV
3 V0.751.65
VhysInput voltage hysteresis (VIT+ – VIT–)3 V0.31V
RPullPullup or pulldown resistorFor pullup: VIN = VSS
For pulldown: VIN = VCC
3 V203550
CIInput capacitanceVIN = VSS or VCC 5pF

5.10 Leakage Current, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCMINMAXUNIT
Ilkg(Px.y)High-impedance leakage currentSee (1) (2)3 V±50nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled.

5.11 Outputs, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
VOHHigh-level output voltageI(OHmax) = –6 mA(1)3 VVCC – 0.3V
VOLLow-level output voltageI(OLmax) = 6 mA(1)3 VVSS + 0.3V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.

5.12 Output Frequency, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
fPx.yPort output frequency (with load)Px.y, CL = 20 pF, RL = 1 kΩ(1) (2)3 V12MHz
fPort_CLKClock output frequencyPx.y, CL = 20 pF(2)3 V16MHz
(1) A resistive divider with two 50-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the divider.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

5.13 Typical Characteristics – Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_iol_vol_2p2v_las694.gif Figure 5-6 Typical Low-Level Output Current vs Low-Level Output Voltage
MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_ioh_voh_2p2v_las694.gif Figure 5-8 Typical High-Level Output Current vs High-Level Output Voltage
MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_iol_vol_3v_las694.gif Figure 5-7 Typical Low-Level Output Current vs Low-Level Output Voltage
MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_ioh_voh_3v_las694.gif Figure 5-9 Typical High-Level Output Current vs High-Level Output Voltage

5.14 Pin-Oscillator Frequency – Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
foP1.xPort output oscillation frequencyP1.y, CL = 10 pF, RL = 100 kΩ(1)(2)3 V1400kHz
P1.y, CL = 20 pF, RL = 100 kΩ(1)(2)900
foP2.xPort output oscillation frequencyP2.0 to P2.5, CL = 10 pF, RL = 100 kΩ(1)(2)3 V1800kHz
P2.0 to P2.5, CL = 20 pF, RL = 100 kΩ(1)(2)1000
foP2.6/7Port output oscillation frequencyP2.6 and P2.7, CL = 20 pF, RL = 100 kΩ(1)(2)3 V700kHz
foP3.xPort output oscillation frequencyP3.y, CL = 10 pF, RL = 100 kΩ(1)(2)3 V1800kHz
P3.y, CL = 20 pF, RL = 100 kΩ(1)(2)1000
(1) A resistive divider with two 50-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the divider.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

5.15 Typical Characteristics – Pin-Oscillator Frequency

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_fosc_cload_vcc3_las734.gif

NOTE:

One output active at a time.
Figure 5-10 Typical Oscillating Frequency vs Load Capacitance
MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_fosc_cload_vcc2p2_las734.gif

NOTE:

One output active at a time.
Figure 5-11 Typical Oscillating Frequency vs Load Capacitance

5.16 POR, BOR(1)(2)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
VCC(start)See Figure 5-12dVCC/dt ≤ 3 V/s0.7 V(B_IT--)V
V(B_IT–)See Figure 5-12 through Figure 5-14dVCC/dt ≤ 3 V/s1.35V
Vhys(B_IT–)See Figure 5-12dVCC/dt ≤ 3 V/s140mV
td(BOR)See Figure 5-122000µs
t(reset)Pulse duration needed at RST/NMI pin to accepted reset internally 2.2 V2µs
(1) The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–) + Vhys(B_IT–) is ≤ 1.8 V.
(2) During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT–) + Vhys(B_IT–). The default DCO settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 por_bor_vcc_las694.gif Figure 5-12 POR and BOR vs Supply Voltage
MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 vccdrop_square_las694.gif Figure 5-13 VCC(drop) Level With a Square Voltage Drop to Generate a POR or BOR Signal
MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 vccdrop_triangle_las694.gif Figure 5-14 VCC(drop) Level With a Triangle Voltage Drop to Generate a POR or BOR Signal

5.17 Main DCO Characteristics

  • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15.
  • DCO control bits DCOx have a step size as defined by parameter SDCO.
  • Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 eq_faverage_las694.gif

5.18 DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
VCCSupply voltageRSELx < 141.83.6V
RSELx = 142.23.6
RSELx = 1533.6
fDCO(0,0)DCO frequency (0, 0)RSELx = 0, DCOx = 0, MODx = 03 V0.060.14MHz
fDCO(0,3)DCO frequency (0, 3)RSELx = 0, DCOx = 3, MODx = 03 V0.070.17MHz
fDCO(1,3)DCO frequency (1, 3)RSELx = 1, DCOx = 3, MODx = 03 V0.15MHz
fDCO(2,3)DCO frequency (2, 3)RSELx = 2, DCOx = 3, MODx = 03 V0.21MHz
fDCO(3,3)DCO frequency (3, 3)RSELx = 3, DCOx = 3, MODx = 03 V0.30MHz
fDCO(4,3)DCO frequency (4, 3)RSELx = 4, DCOx = 3, MODx = 03 V0.41MHz
fDCO(5,3)DCO frequency (5, 3)RSELx = 5, DCOx = 3, MODx = 03 V0.58MHz
fDCO(6,3)DCO frequency (6, 3)RSELx = 6, DCOx = 3, MODx = 03 V0.541.06MHz
fDCO(7,3)DCO frequency (7, 3)RSELx = 7, DCOx = 3, MODx = 03 V0.801.50MHz
fDCO(8,3)DCO frequency (8, 3)RSELx = 8, DCOx = 3, MODx = 03 V1.6MHz
fDCO(9,3)DCO frequency (9, 3)RSELx = 9, DCOx = 3, MODx = 03 V2.3MHz
fDCO(10,3)DCO frequency (10, 3)RSELx = 10, DCOx = 3, MODx = 03 V3.4MHz
fDCO(11,3)DCO frequency (11, 3)RSELx = 11, DCOx = 3, MODx = 03 V4.25MHz
fDCO(12,3)DCO frequency (12, 3)RSELx = 12, DCOx = 3, MODx = 03 V4.307.30MHz
fDCO(13,3)DCO frequency (13, 3)RSELx = 13, DCOx = 3, MODx = 03 V6.009.60MHz
fDCO(14,3)DCO frequency (14, 3)RSELx = 14, DCOx = 3, MODx = 03 V8.6013.9MHz
fDCO(15,3)DCO frequency (15, 3)RSELx = 15, DCOx = 3, MODx = 03 V12.018.5MHz
fDCO(15,7)DCO frequency (15, 7)RSELx = 15, DCOx = 7, MODx = 03 V16.026.0MHz
SRSELFrequency step between range RSEL and RSEL+1SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)3 V1.35ratio
SDCOFrequency step between tap DCO and DCO+1SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)3 V1.08ratio
Duty cycleMeasured at SMCLK output3 V50%

5.19 Calibrated DCO Frequencies, Tolerance

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSTAVCCMINTYPMAXUNIT
1-MHz tolerance over temperature(1)BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
0°C to 85°C3 V–3%±0.5%+3%
1-MHz tolerance over VCCBCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
30°C1.8 V to 3.6 V–3%±2%+3%
1-MHz tolerance overallBCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
–40°C to 85°C1.8 V to 3.6 V–6%±3%+6%
8-MHz tolerance over temperature(1)BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
0°C to 85°C3 V–3%±0.5%+3%
8-MHz tolerance over VCCBCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
30°C2.2 V to 3.6 V–3%±2%+3%
8-MHz tolerance overallBCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
–40°C to 85°C2.2 V to 3.6 V–6%±3%+6%
12-MHz tolerance over temperature(1)BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
0°C to 85°C3 V–3%±0.5%+3%
12-MHz tolerance over VCCBCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
30°C2.7 V to 3.6 V–3%±2%+3%
12-MHz tolerance overallBCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
–40°C to 85°C2.7 V to 3.6 V–6%±3%+6%
16-MHz tolerance over temperature(1)BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
0°C to 85°C3 V–3%±0.5%+3%
16-MHz tolerance over VCCBCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
30°C3.3 V to 3.6 V–3%±2%+3%
16-MHz tolerance overallBCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
–40°C to 85°C3.3 V to 3.6 V–6%±3%+6%
(1) This is the frequency change from the measured frequency at 30°C over temperature.

5.20 Wake-up Times From Lower-Power Modes (LPM3, LPM4)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
tDCO,LPM3/4DCO clock wake-up time from LPM3 or LPM4(1)BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz3 V1.5µs
tCPU,LPM3/4CPU wake-up time from LPM3 or LPM4(2)1/fMCLK +
tClock,LPM3/4
(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK).
(2) Parameter applicable only if DCOCLK is used for MCLK.

5.21 Typical Characteristics, DCO Clock Wake-up Time From LPM3 or LPM4

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_tdcowake_fdco_las694.gif Figure 5-15 DCO Wake-up Time From LPM3 vs DCO Frequency

5.22 Crystal Oscillator, XT1, Low-Frequency Mode(4)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
fLFXT1,LFLFXT1 oscillator crystal frequency, LF mode 0, 1XTS = 0, LFXT1Sx = 0 or 11.8 V to 3.6 V32768Hz
fLFXT1,LF,logic LFXT1 oscillator logic level square-wave input frequency, LF modeXTS = 0, XCAPx = 0, LFXT1Sx = 31.8 V to 3.6 V100003276850000Hz
OALFOscillation allowance for LF crystalsXTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
200
CL,effIntegrated effective load capacitance, LF mode(1)XTS = 0, XCAPx = 01pF
XTS = 0, XCAPx = 15.5
XTS = 0, XCAPx = 28.5
XTS = 0, XCAPx = 311
Duty cycle, LF modeXTS = 0, Measured at P2.0/ACLK,
fLFXT1,LF = 32768 Hz
2.2 V30%50%70%
fFault,LFOscillator fault frequency, LF mode(3)XTS = 0, XCAPx = 0, LFXT1Sx = 3(2)2.2 V1010000Hz
(1) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal.
(2) Measured with logic-level input frequency but also applies to operation with crystals.
(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag.
(4) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
  • Keep the trace between the device and the crystal as short as possible.
  • Design a good ground plane around the oscillator pins.
  • Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
  • Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
  • Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
  • If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
  • Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter.

5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTAVCCMINTYPMAXUNIT
fVLOVLO frequency–40°C to 85°C3 V41220kHz
dfVLO/dTVLO frequency temperature drift–40°C to 85°C3 V0.5%/°C
dfVLO/dVCCVLO frequency supply voltage drift25°C1.8 V to 3.6 V4%/V

5.24 Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
fTATimer_A input clock frequencySMCLK, duty cycle = 50% ±10%fSYSTEMMHz
tTA,capTimer_A capture timingTA0, TA13 V20ns

5.25 USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
fUSCIUSCI input clock frequencySMCLK, duty cycle = 50% ±10%fSYSTEMMHz
fmax,BITCLKMaximum BITCLK clock frequency (equals baud rate in MBaud)(1)3 V2MHz
tτUART receive deglitch time(2)3 V50100600ns
(1) The DCO wake-up time must be considered in LPM3 and LPM4 for baud rates above 1 MHz.
(2) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time.

5.26 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-16 and Figure 5-17)
PARAMETERTEST CONDITIONSVCCMINMAXUNIT
fUSCIUSCI input clock frequencySMCLK, duty cycle = 50% ±10%fSYSTEMMHz
tSU,MISOMI input data setup time3 V75ns
tHD,MISOMI input data hold time3 V0ns
tVALID,MOSIMO output data valid timeUCLK edge to SIMO valid, CL = 20 pF3 V20ns
MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 t_usci_spi_master_ckph0_las734.gif Figure 5-16 SPI Master Mode, CKPH = 0
MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 t_usci_spi_master_ckph1_las734.gif Figure 5-17 SPI Master Mode, CKPH = 1

5.27 USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18 and Figure 5-19)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
tSTE,LEADSTE lead time, STE low to clock3 V50ns
tSTE,LAGSTE lag time, Last clock to STE high3 V10ns
tSTE,ACCSTE access time, STE low to SOMI data out3 V50ns
tSTE,DISSTE disable time, STE high to SOMI high impedance3 V50ns
tSU,SISIMO input data setup time3 V15ns
tHD,SISIMO input data hold time3 V10ns
tVALID,SOSOMI output data valid timeUCLK edge to SOMI valid,
CL = 20 pF
3 V5075ns
MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 t_usci_spi_slave_ckph0_las734.gif Figure 5-18 SPI Slave Mode, CKPH = 0
MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 t_usci_spi_slave_ckph1_las734.gif Figure 5-19 SPI Slave Mode, CKPH = 1

5.28 USCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-20)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
fUSCIUSCI input clock frequencySMCLK, duty cycle = 50% ±10%fSYSTEMMHz
fSCLSCL clock frequency3 V0400kHz
tHD,STAHold time (repeated) STARTfSCL ≤ 100 kHz3 V4.0µs
fSCL > 100 kHz0.6
tSU,STASetup time for a repeated STARTfSCL ≤ 100 kHz3 V4.7µs
fSCL > 100 kHz0.6
tHD,DATData hold time3 V0ns
tSU,DATData setup time3 V250ns
tSU,STOSetup time for STOP3 V4.0µs
tSPPulse duration of spikes suppressed by input filter3 V50100600ns
MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 t_usci_i2c_las734.gif Figure 5-20 I2C Mode Timing

5.29 10-Bit ADC, Power Supply and Input Range Conditions (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETERTEST CONDITIONSTAVCCMINTYPMAXUNIT
VCCAnalog supply voltageVSS = 0 V2.23.6V
VAxAnalog input voltage(2)All Ax terminals, Analog inputs selected in ADC10AE register3 V0VCCV
IADC10ADC10 supply current(3)fADC10CLK = 5.0 MHz,
ADC10ON = 1, REFON = 0, ADC10SHT0 = 1, ADC10SHT1 = 0, ADC10DIV = 0
25°C3 V0.6mA
IREF+Reference supply current, reference buffer disabled(4)fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
25°C3 V0.25mA
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
0.25
IREFB,0Reference buffer supply current with ADC10SR  = 0(4)fADC10CLK = 5.0 MHz,
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR  = 0
25°C3 V1.1mA
IREFB,1Reference buffer supply current with ADC10SR  = 1(4)fADC10CLK = 5.0 MHz,
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR  = 1
25°C3 V0.5mA
CIInput capacitanceOnly one terminal Ax can be selected at one time25°C3 V27pF
RIInput MUX ON resistance0 V ≤ VAx ≤ VCC25°C3 V1000Ω
(1) The leakage current is defined in the leakage current table with Px.y/Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
(3) The internal reference supply current is not included in current consumption parameter IADC10.
(4) The internal reference current is supplied through terminal VCC. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

5.30 10-Bit ADC, Built-In Voltage Reference (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
VCC,REF+Positive built-in reference analog supply voltage rangeIVREF+ ≤ 1 mA, REF2_5V = 02.2V
IVREF+ ≤ 1 mA, REF2_5V = 12.9
VREF+Positive built-in reference voltageIVREF+ ≤ IVREF+max, REF2_5V = 03 V1.411.51.59V
IVREF+ ≤ IVREF+max, REF2_5V = 12.352.52.65
ILD,VREF+Maximum VREF+ load current3 V±1mA
VREF+ load regulationIVREF+ = 500 µA ±100 µA,
Analog input voltage VAx ≈ 0.75 V,
REF2_5V = 0
3 V±2LSB
IVREF+ = 500 µA ±100 µA,
Analog input voltage VAx ≈ 1.25 V,
REF2_5V = 1
±2
VREF+ load regulation response timeIVREF+ = 100 µA → 900 µA,
VAx ≈ 0.5 × VREF+,
Error of conversion result ≤ 1 LSB,
ADC10SR = 0
3 V400ns
CVREF+Maximum capacitance at pin VREF+IVREF+ ≤ ±1 mA, REFON = 1, REFOUT = 13 V100pF
TCREF+Temperature coefficientIVREF+ = const with 0 mA ≤ IVREF+ ≤ 1 mA3 V±100ppm/ °C
tREFONSettling time of internal reference voltage to 99.9% VREFIVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 → 1
3.6 V30µs
tREFBURSTSettling time of reference buffer to 99.9% VREFIVREF+ = 0.5 mA,
REF2_5V = 1, REFON = 1,
REFBURST = 1, ADC10SR = 0
3 V2µs

5.31 10-Bit ADC, External Reference(1) (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
VEREF+Positive external reference input voltage range (2)VEREF+ > VEREF–,
SREF1 = 1, SREF0 = 0
1.4VCCV
VEREF– ≤ VEREF+ ≤ VCC – 0.15 V,
SREF1 = 1, SREF0 = 1 (3)
1.43
VEREF–Negative external reference input voltage range (4)VEREF+ > VEREF– 01.2V
ΔVEREFDifferential external reference input voltage range,
ΔVEREF = VEREF+ – VEREF–
VEREF+ > VEREF– (5)1.4VCCV
IVEREF+Static input current into VEREF+0 V ≤ VEREF+ ≤ VCC,
SREF1 = 1, SREF0 = 0
3 V±1µA
0 V ≤ VEREF+ ≤ VCC – 0.15 V ≤ 3 V,
SREF1 = 1, SREF0 = 1(3)
3 V0
IVEREF–Static input current into VEREF–0 V ≤ VEREF– ≤ VCC3 V±1µA
(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements.
(3) Under this condition, the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
(4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements.
(5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements.

5.32 10-Bit ADC, Timing Parameters (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
fADC10CLKADC10 input clock frequencyFor specified performance of ADC10 linearity parametersADC10SR = 03 V0.456.3MHz
ADC10SR = 10.451.5
fADC10OSCADC10 built-in oscillator frequencyADC10DIVx = 0, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
3 V3.76.3MHz
tCONVERTConversion timeADC10 built-in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
3 V2.063.51µs
fADC10CLK from ACLK, MCLK, or SMCLK: ADC10SSELx ≠ 013 ×
ADC10DIV ×
1 / fADC10CLK
tADC10ONTurnon settling time of the ADC  (1)100ns
(1) The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already settled.

5.33 10-Bit ADC, Linearity Parameters (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
EIIntegral linearity error3 V±1LSB
EDDifferential linearity error3 V±1LSB
EOOffset errorSource impedance RS < 100 Ω3 V±1LSB
EGGain error3 V±1.1±2LSB
ETTotal unadjusted error3 V±2±5LSB

5.34 10-Bit ADC, Temperature Sensor and Built-In VMID (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
ISENSORTemperature sensor supply current(1)REFON = 0, INCHx = 0Ah, TA = 25°C3 V60µA
TCSENSORADC10ON = 1, INCHx = 0Ah (2)3 V3.55mV/°C
tSensor(sample)Sample time required if channel 10 is selected (3)ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
3 V30µs
IVMIDCurrent into divider at channel 11ADC10ON = 1, INCHx = 0Bh3 V (4) µA
VMIDVCC divider at channel 11ADC10ON = 1, INCHx = 0Bh,
VMID ≈ 0.5 × VCC
3 V1.5V
tVMID(sample)Sample time required if channel 11 is selected (5)ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
3 V1220ns
(1) The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor input (INCH = 0Ah).
(2) The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor (273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
(4) No additional current is needed. The VMID is used during sampling.
(5) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.

5.35 Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
VCC(PGM/ERASE)Program and erase supply voltage2.23.6V
fFTGFlash timing generator frequency257476kHz
IPGMSupply current from VCC during program2.2 V, 3.6 V15mA
IERASESupply current from VCC during erase2.2 V, 3.6 V17mA
tCPTCumulative program time(1)2.2 V, 3.6 V10ms
tCMEraseCumulative mass erase time2.2 V, 3.6 V20ms
Program and erase endurance104105cycles
tRetentionData retention durationTJ = 25°C100years
tWordWord or byte program timeSee (2) 30tFTG
tBlock, 0Block program time for first byte or wordSee (2) 25tFTG
tBlock, 1-63Block program time for each additional byte or wordSee (2) 18tFTG
tBlock, EndBlock program end-sequence wait timeSee (2) 6tFTG
tMass EraseMass erase timeSee (2) 10593tFTG
tSeg EraseSegment erase timeSee (2) 4819tFTG
(1) Do not exceed the cumulative program time when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word or byte write and block write modes.
(2) These values are hardwired into the state machine of the flash controller (tFTG = 1/fFTG).

5.36 RAM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSMINMAXUNIT
V(RAMh)RAM retention supply voltage (1)CPU halted1.6V
(1) This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition.

5.37 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERVCCMINTYPMAXUNIT
fSBWSpy-Bi-Wire input frequency2.2 V020MHz
tSBW,LowSpy-Bi-Wire low clock pulse duration2.2 V0.02515µs
tSBW,EnSpy-Bi-Wire enable time
(TEST high to acceptance of first clock edge(1))
2.2 V1µs
tSBW,RetSpy-Bi-Wire return to normal operation time2.2 V15100µs
fTCKTCK input frequency(2)2.2 V05MHz
RInternalInternal pulldown resistance on TEST2.2 V256090
(1) Tools that access the Spy-Bi-Wire interface must wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before applying the first SBWCLK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.

5.38 JTAG Fuse(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSMINMAXUNIT
VCC(FB)Supply voltage during fuse-blow conditionTA = 25°C2.5V
VFBVoltage level on TEST for fuse blow67V
IFBSupply current into TEST during fuse blow100mA
tFBTime to blow fuse1ms
(1) After the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation features is possible, and JTAG is switched to bypass mode.