SLAS734G April 2011  – April 2016 MSP430G2203 , MSP430G2233 , MSP430G2303 , MSP430G2333 , MSP430G2403 , MSP430G2433 , MSP430G2533

PRODUCTION DATA. 

  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagrams
    2. 4.2Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5 Typical Characteristics, Active Mode Supply Current (Into VCC)
    6. 5.6 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    7. 5.7 Typical Characteristics, Low-Power Mode Supply Currents
    8. 5.8 Thermal Resistance Characteristics
    9. 5.9 Schmitt-Trigger Inputs, Ports Px
    10. 5.10Leakage Current, Ports Px
    11. 5.11Outputs, Ports Px
    12. 5.12Output Frequency, Ports Px
    13. 5.13Typical Characteristics - Outputs
    14. 5.14Pin-Oscillator Frequency - Ports Px
    15. 5.15Typical Characteristics - Pin-Oscillator Frequency
    16. 5.16POR, BOR
    17. 5.17Main DCO Characteristics
    18. 5.18DCO Frequency
    19. 5.19Calibrated DCO Frequencies, Tolerance
    20. 5.20Wake-up Times From Lower-Power Modes (LPM3, LPM4)
    21. 5.21Typical Characteristics, DCO Clock Wake-up Time From LPM3 or LPM4
    22. 5.22Crystal Oscillator, XT1, Low-Frequency Mode
    23. 5.23Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    24. 5.24Timer_A
    25. 5.25USCI (UART Mode)
    26. 5.26USCI (SPI Master Mode)
    27. 5.27USCI (SPI Slave Mode)
    28. 5.28USCI (I2C Mode)
    29. 5.2910-Bit ADC, Power Supply and Input Range Conditions (MSP430G2x33 Only)
    30. 5.3010-Bit ADC, Built-In Voltage Reference (MSP430G2x33 Only)
    31. 5.3110-Bit ADC, External Reference (MSP430G2x33 Only)
    32. 5.3210-Bit ADC, Timing Parameters (MSP430G2x33 Only)
    33. 5.3310-Bit ADC, Linearity Parameters (MSP430G2x33 Only)
    34. 5.3410-Bit ADC, Temperature Sensor and Built-In VMID (MSP430G2x33 Only)
    35. 5.35Flash Memory
    36. 5.36RAM
    37. 5.37JTAG and Spy-Bi-Wire Interface
    38. 5.38JTAG Fuse
  6. 6Detailed Description
    1. 6.1 CPU
    2. 6.2 Instruction Set
    3. 6.3 Operating Modes
    4. 6.4 Interrupt Vector Addresses
    5. 6.5 Special Function Registers (SFRs)
    6. 6.6 Memory Organization
    7. 6.7 Bootloader (BSL)
    8. 6.8 Flash Memory
    9. 6.9 Peripherals
      1. 6.9.1Oscillator and System Clock
      2. 6.9.2Calibration Data Stored in Information Memory Segment A
      3. 6.9.3Brownout
      4. 6.9.4Digital I/O
      5. 6.9.5WDT+ Watchdog Timer
      6. 6.9.6Timer_A3 (TA0, TA1)
      7. 6.9.7Universal Serial Communications Interface (USCI)
      8. 6.9.8ADC10 (MSP430G2x33 Only)
      9. 6.9.9Peripheral File Map
    10. 6.10I/O Port Diagrams
      1. 6.10.1Port P1 Pin Diagram: P1.0 to P1.2, Input/Output With Schmitt Trigger
      2. 6.10.2Port P1 Pin Diagram: P1.3, Input/Output With Schmitt Trigger
      3. 6.10.3Port P1 Pin Diagram: P1.4, Input/Output With Schmitt Trigger
      4. 6.10.4Port P1 Pin Diagram: P1.5 to P1.7, Input/Output With Schmitt Trigger
      5. 6.10.5Port P2 Pin Diagram: P2.0 to P2.5, Input/Output With Schmitt Trigger
      6. 6.10.6Port P2 Pin Diagram: P2.6, Input/Output With Schmitt Trigger
      7. 6.10.7Port P2 Pin Diagram: P2.7, Input/Output With Schmitt Trigger
      8. 6.10.8Port P3 Pin Diagram: P3.0 to P3.7, Input/Output With Schmitt Trigger (RHB and PW28 Package Only)
  7. 7Device and Documentation Support
    1. 7.1Getting Started and Next Steps
    2. 7.2Device Nomenclature
    3. 7.3Tools and Software
    4. 7.4Documentation Support
    5. 7.5Related Links
    6. 7.6Community Resources
    7. 7.7Trademarks
    8. 7.8Electrostatic Discharge Caution
    9. 7.9Glossary
  8. 8Mechanical, Packaging, and Orderable Information

4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the pinout for the MSP430G2x03 and MSP430G2x33 devices in the 20-pin N or PW package.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 pinout_pw_n20_las734.gif

NOTE:

ADC10 is available on MSP430G2x33 devices only.

NOTE:

The pulldown resistors of port P3 should be enabled by setting P3REN.x = 1.
Figure 4-1 20-Pin N or PW Package (Top View), MSP430G2x03 and MSP430G2x33

Figure 4-2 shows the pinout for the MSP430G2x03 and MSP430G2x33 devices in the 28-pin PW package.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 pinout_pw28_las734.gif

NOTE:

ADC10 is available on MSP430G2x33 devices only.
Figure 4-2 28-Pin PW Package (Top View), MSP430G2x03 and MSP430G2x33

Figure 4-3 shows the pinout for the MSP430G2x03 and MSP430G2x33 devices in the 32-pin RHB package.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 pinout_rhb32_las734.gif

NOTE:

ADC10 is available on MSP430G2x33 devices only.
Figure 4-3 32-Pin RHB Package (Top View), MSP430G2x03 and MSP430G2x33

4.2 Signal Descriptions

Table 4-1 describes the signals.

Table 4-1 Terminal Functions

TERMINALI/ODESCRIPTION
NAMENO.
PW20, N20PW28RHB32
P1.0/2231I/OGeneral-purpose digital I/O pin
TA0CLK/Timer0_A, clock signal TACLK input
ACLK/ACLK signal output
A0ADC10 analog input A0(1)
P1.1/331I/OGeneral-purpose digital I/O pin
TA0.0/Timer0_A, capture: CCI0A input, compare: Out0 output / BSL transmit
UCA0RXD/USCI_A0 receive data input in UART mode
UCA0SOMI/USCI_A0 slave data out/master in SPI mode
A1ADC10 analog input A1(1)
P1.2/442I/OGeneral-purpose digital I/O pin
TA0.1/Timer0_A, capture: CCI1A input, compare: Out1 output
UCA0TXD/USCI_A0 transmit data output in UART mode
UCA0SIMO/USCI_A0 slave data in/master out in SPI mode
A2ADC10 analog input A2(1)
P1.3/553I/OGeneral-purpose digital I/O pin
ADC10CLK/ADC10, conversion clock output(1)
A3/ADC10 analog input A3(1)
VREF-/VEREF-ADC10 negative reference voltage (1)
P1.4/664I/OGeneral-purpose digital I/O pin
SMCLK/SMCLK signal output
UCB0STE/USCI_B0 slave transmit enable
UCA0CLK/USCI_A0 clock input/output
A4/ADC10 analog input A4(1)
VREF+/VEREF+ADC10 positive reference voltage(1)
TCKJTAG test clock, input terminal for device programming and test
P1.5/775I/OGeneral-purpose digital I/O pin
TA0.0/Timer0_A, compare: Out0 output / BSL receive
UCB0CLK/USCI_B0 clock input/output
UCA0STE/USCI_A0 slave transmit enable
A5/ADC10 analog input A5(1)
TMSJTAG test mode select, input terminal for device programming and test
P1.6/142221I/OGeneral-purpose digital I/O pin
TA0.1/Timer0_A, compare: Out1 output
A6/ADC10 analog input A6(1)
UCB0SOMI/USCI_B0 slave out/master in SPI mode,
UCB0SCL/USCI_B0 SCL I2C clock in I2C mode
TDI/TCLKJTAG test data input or test clock input during programming and test
P1.7/152322I/OGeneral-purpose digital I/O pin
A7/ADC10 analog input A7(1)
UCB0SIMO/USCI_B0 slave in/master out in SPI mode
UCB0SDA/USCI_B0 SDA I2C data in I2C mode
TDO/TDIJTAG test data output terminal or test data input during programming and test(3)
P2.0/8109I/OGeneral-purpose digital I/O pin
TA1.0Timer1_A, capture: CCI0A input, compare: Out0 output
P2.1/91110I/OGeneral-purpose digital I/O pin
TA1.1Timer1_A, capture: CCI1A input, compare: Out1 output
P2.2/101211I/OGeneral-purpose digital I/O pin
TA1.1Timer1_A, capture: CCI1B input, compare: Out1 output
P2.3/111615I/OGeneral-purpose digital I/O pin
TA1.0Timer1_A, capture: CCI0B input, compare: Out0 output
P2.4/121716I/OGeneral-purpose digital I/O pin
TA1.2Timer1_A, capture: CCI2A input, compare: Out2 output
P2.5/131817I/OGeneral-purpose digital I/O pin
TA1.2Timer1_A, capture: CCI2B input, compare: Out2 output
XIN/192726I/OInput terminal of crystal oscillator
P2.6/General-purpose digital I/O pin
TA0.1Timer0_A, compare: Out1 output
XOUT/182625I/OOutput terminal of crystal oscillator(2)
P2.7General-purpose digital I/O pin
P3.0/-97I/OGeneral-purpose digital I/O pin
TA0.2Timer0_A, capture: CCI2A input, compare: Out2 output
P3.1/-86I/OGeneral-purpose digital I/O pin
TA1.0Timer1_A, compare: Out0 output
P3.2/-1312I/OGeneral-purpose digital I/O pin
TA1.1Timer1_A, compare: Out1 output
P3.3/-1413I/OGeneral-purpose digital I/O
TA1.2Timer1_A, compare: Out2 output
P3.4/-1514I/OGeneral-purpose digital I/O
TA0.0Timer0_A, compare: Out0 output
P3.5/-1918I/OGeneral-purpose digital I/O
TA0.1Timer0_A, compare: Out1 output
P3.6/-2019I/OGeneral-purpose digital I/O
TA0.2Timer0_A, compare: Out2 output
P3.7/-2120I/OGeneral-purpose digital I/O
TA1CLKTimer1_A, clock signal TACLK input
RST/162423IReset
NMI/Nonmaskable interrupt input
SBWTDIOSpy-Bi-Wire test data input/output during programming and test
TEST/172524ISelects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.
SBWTCKSpy-Bi-Wire test clock input during programming and test
AVCCNANA29NAAnalog supply voltage
DVCC1130NADigital supply voltage
DVSS202827, 28NAGround reference
NCNANA8, 32NANot connected
QFN PadNANAPadNAQFN package pad connection to VSS recommended.
(1) MSP430G2x33 devices only
(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset.
(3) TDO or TDI is selected by JTAG instruction.