SLAS826G March 2015  – September 2017 MSP432P401M , MSP432P401R

PRODUCTION DATA. 

  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagrams
    2. 4.2Pin Attributes
    3. 4.3Signal Descriptions
    4. 4.4Pin Multiplexing
    5. 4.5Buffer Types
    6. 4.6Connection for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Recommended External Components
    5. 5.5 Operating Mode VCC Ranges
    6. 5.6 Operating Mode CPU Frequency Ranges
    7. 5.7 Operating Mode Peripheral Frequency Ranges
    8. 5.8 Operating Mode Execution Frequency vs Flash Wait-State Requirements
    9. 5.9 Current Consumption During Device Reset
    10. 5.10Current Consumption in LDO-Based Active Modes - Dhrystone 2.1 Program
    11. 5.11Current Consumption in DC-DC-Based Active Modes - Dhrystone 2.1 Program
    12. 5.12Current Consumption in Low-Frequency Active Modes - Dhrystone 2.1 Program
    13. 5.13Typical Characteristics of Active Mode Currents for CoreMark Program
    14. 5.14Typical Characteristics of Active Mode Currents for Prime Number Program
    15. 5.15Typical Characteristics of Active Mode Currents for Fibonacci Program
    16. 5.16Typical Characteristics of Active Mode Currents for While(1) Program
    17. 5.17Typical Characteristics of Low-Frequency Active Mode Currents for CoreMark Program
    18. 5.18Current Consumption in LDO-Based LPM0 Modes
    19. 5.19Current Consumption in DC-DC-Based LPM0 Modes
    20. 5.20Current Consumption in Low-Frequency LPM0 Modes
    21. 5.21Current Consumption in LPM3, LPM4 Modes
    22. 5.22Current Consumption in LPM3.5, LPM4.5 Modes
    23. 5.23Current Consumption of Digital Peripherals
    24. 5.24Thermal Resistance Characteristics
    25. 5.25Timing and Switching Characteristics
      1. 5.25.1 Reset Timing
      2. 5.25.2 Peripheral Register Access Timing
      3. 5.25.3 Mode Transition Timing
      4. 5.25.4 Clock Specifications
      5. 5.25.5 Power Supply System
      6. 5.25.6 Digital I/Os
        1. 5.25.6.1Typical Characteristics, Normal-Drive I/O Outputs at 3.0 V and 2.2 V
        2. 5.25.6.2Typical Characteristics, High-Drive I/O Outputs at 3.0 V and 2.2 V
        3. 5.25.6.3Typical Characteristics, Pin-Oscillator Frequency
      7. 5.25.7 Precision ADC
        1. 5.25.7.1Typical Characteristics of ADC
      8. 5.25.8 REF_A
      9. 5.25.9 Comparator_E
      10. 5.25.10eUSCI
      11. 5.25.11Timers
      12. 5.25.12Memories
      13. 5.25.13Emulation and Debug
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Processor and Execution Features
      1. 6.2.1Floating-Point Unit
      2. 6.2.2Memory Protection Unit
      3. 6.2.3Nested Vectored Interrupt Controller (NVIC)
      4. 6.2.4SysTick
      5. 6.2.5Debug and Trace Features
    3. 6.3 Memory Map
      1. 6.3.1Code Zone Memory Map
        1. 6.3.1.1Flash Memory Region
        2. 6.3.1.2SRAM Region
        3. 6.3.1.3ROM Region
      2. 6.3.2SRAM Zone Memory Map
        1. 6.3.2.1SRAM Region
        2. 6.3.2.2SRAM Bit-Band Alias Region
      3. 6.3.3Peripheral Zone Memory Map
        1. 6.3.3.1Peripheral Region
        2. 6.3.3.2Peripheral Bit Band Alias Region
      4. 6.3.4Debug and Trace Peripheral Zone
    4. 6.4 Memories on the MSP432P401x
      1. 6.4.1Flash Memory
        1. 6.4.1.1Flash Main Memory (0x0000_0000 to 0x0003_FFFF)
        2. 6.4.1.2Flash Information Memory (0x0020_0000 to 0x0020_3FFF)
        3. 6.4.1.3Flash Operation
      2. 6.4.2SRAM
        1. 6.4.2.1SRAM Bank Enable Configuration
        2. 6.4.2.2SRAM Bank Retention Configuration and Backup Memory
      3. 6.4.3ROM
    5. 6.5 DMA
      1. 6.5.1DMA Source Mapping
      2. 6.5.2DMA Completion Interrupts
      3. 6.5.3DMA Access Privileges
    6. 6.6 Memory Map Access Details
      1. 6.6.1Master and Slave Access Priority Settings
      2. 6.6.2Memory Map Access Response
    7. 6.7 Interrupts
      1. 6.7.1NMI
      2. 6.7.2Device-Level User Interrupts
    8. 6.8 System Control
      1. 6.8.1Device Resets
        1. 6.8.1.1Power On/Off Reset (POR)
        2. 6.8.1.2Reboot Reset
        3. 6.8.1.3Hard Reset
        4. 6.8.1.4Soft Reset
      2. 6.8.2Power Supply System (PSS)
        1. 6.8.2.1VCCDET
        2. 6.8.2.2Supply Supervisor and Monitor for High Side (SVSMH)
        3. 6.8.2.3Core Voltage Regulator
      3. 6.8.3Power Control Manager (PCM)
      4. 6.8.4Clock System (CS)
        1. 6.8.4.1LFXT
        2. 6.8.4.2HFXT
        3. 6.8.4.3DCO
        4. 6.8.4.4Very Low-Power Low-Frequency Oscillator (VLO)
        5. 6.8.4.5Low-Frequency Reference Oscillator (REFO)
        6. 6.8.4.6Module Oscillator (MODOSC)
        7. 6.8.4.7System Oscillator (SYSOSC)
        8. 6.8.4.8Fail-Safe Mechanisms
      5. 6.8.5System Controller (SYSCTL)
    9. 6.9 Peripherals
      1. 6.9.1 Digital I/O
        1. 6.9.1.1Glitch Filtering on Digital I/Os
      2. 6.9.2 Port Mapping Controller (PMAPCTL)
        1. 6.9.2.1Port Mapping Definitions
      3. 6.9.3 Timer_A
        1. 6.9.3.1Timer_A Signal Connection Tables
      4. 6.9.4 Timer32
      5. 6.9.5 Enhanced Universal Serial Communication Interface (eUSCI)
      6. 6.9.6 Real-Time Clock (RTC_C)
      7. 6.9.7 Watchdog Timer (WDT_A)
      8. 6.9.8 Precision ADC
      9. 6.9.9 Comparator_E (COMP_E)
      10. 6.9.10Shared Reference (REF_A)
      11. 6.9.11CRC32
      12. 6.9.12AES256 Accelerator
      13. 6.9.13True Random Seed
    10. 6.10Code Development and Debug
      1. 6.10.1JTAG and SWD Based Development, Debug, and Trace
      2. 6.10.2Peripheral Halt Control
      3. 6.10.3Bootloader (BSL)
      4. 6.10.4Device Security
    11. 6.11Performance Benchmarks
      1. 6.11.1ULPBench Performance: 192.3 ULPMark-CP
      2. 6.11.2CoreMark/MHz Performance: 3.41
      3. 6.11.3DMIPS/MHz (Dhrystone 2.1) Performance: 1.22
    12. 6.12Input/Output Diagrams
      1. 6.12.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.12.2 Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
      3. 6.12.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 6.12.4 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
      5. 6.12.5 Port P10 (P10.0 to P10.3) Input/Output With Schmitt Trigger
      6. 6.12.6 Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
      7. 6.12.7 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      8. 6.12.8 Port P9 (P9.2 and P9.3) Input/Output With Schmitt Trigger
      9. 6.12.9 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      10. 6.12.10Port P5 (P5.0 to P5.5) Input/Output With Schmitt Trigger
      11. 6.12.11Port P6 (P6.0 and P6.1) Input/Output With Schmitt Trigger
      12. 6.12.12Port P8 (P8.2 to P8.7) Input/Output With Schmitt Trigger
      13. 6.12.13Port P9 (P9.0 and P9.1) Input/Output With Schmitt Trigger
      14. 6.12.14Port P5 (P5.6 and P5.7) Input/Output With Schmitt Trigger
      15. 6.12.15Port P6 (P6.2 to P6.5) Input/Output With Schmitt Trigger
      16. 6.12.16Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
      17. 6.12.17Port P8 (P8.0 and P8.1) Input/Output With Schmitt Trigger
      18. 6.12.18Port P10 (P10.4 and P10.5) Input/Output With Schmitt Trigger
      19. 6.12.19Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      20. 6.12.20Port PJ (PJ.0 and PJ.1) Input/Output With Schmitt Trigger
      21. 6.12.21Port PJ (PJ.2 and PJ.3) Input/Output With Schmitt Trigger
      22. 6.12.22Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      23. 6.12.23Ports SWCLKTCK and SWDIOTMS With Schmitt Trigger
    13. 6.13Device Descriptors (TLV)
    14. 6.14Identification
      1. 6.14.1Revision Identification
      2. 6.14.2Device Identification
      3. 6.14.3ARM Cortex-M4F ROM Table Based Part Number
  7. 7Applications, Implementation, and Layout
    1. 7.1Device Connection and Layout Fundamentals
      1. 7.1.1Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2External Oscillator
      3. 7.1.3General Layout Recommendations
      4. 7.1.4Do's and Don'ts
    2. 7.2Peripheral and Interface-Specific Design Information
      1. 7.2.1Precision ADC Peripheral
        1. 7.2.1.1Partial Schematic
        2. 7.2.1.2Design Requirements
        3. 7.2.1.3Layout Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device and Development Tool Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Export Control Notice
    10. 8.10Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Device Overview

Features

  • Core
    • ARM® 32-Bit Cortex®-M4F CPU With Floating-Point Unit and Memory Protection Unit
    • Frequency up to 48 MHz
    • ULPBench™ Benchmark:
      • 192.3 ULPMark™-CP
    • Performance Benchmark:
      • 3.41 CoreMark/MHz
      • 1.22 DMIPS/MHz (Dhrystone 2.1)
  • Advanced Low-Power Analog Features
    • SAR Analog-To-Digital Converter (ADC) With 16-Bit Precision and up to 1 Msps
      • Differential and Single-Ended Inputs
      • Two Window Comparators
      • Up to 24 Input Channels
    • Internal Voltage Reference With 10-ppm/°C Typical Stability
    • Two Analog Comparators
  • Memories
    • Up to 256KB of Flash Main Memory (Organized Into Two Banks Enabling Simultaneous Read/Execute During Erase)
    • 16KB of Flash Information Memory (Used for BSL, TLV, and Flash Mailbox)
    • Up to 64KB of SRAM (Including 6KB of Backup Memory)
    • 32KB of ROM With MSP432™ Peripheral Driver Libraries
  • Ultra-Low-Power Operating Modes
    • Active: 80 µA/MHz
    • Low-Frequency Active: 83 µA at 128 kHz
    • LPM3 (With RTC): 660 nA
    • LPM3.5 (With RTC): 630 nA
    • LPM4: 500 nA
    • LPM4.5: 25 nA
  • Development Kits and Software (See Tools and Software)
  • Operating Characteristics
    • Wide Supply Voltage Range: 1.62 V to 3.7 V
    • Temperature Range (Ambient): –40°C to 85°C
  • Flexible Clocking Features
    • Tunable Internal DCO (up to 48 MHz)
    • 32.768-kHz Low-Frequency Crystal Support (LFXT)
    • High-Frequency Crystal Support (HFXT) up to 48 MHz
    • Low-Frequency Internal Reference Oscillator (REFO)
    • Very Low-Power Low-Frequency Internal Oscillator (VLO)
    • Module Oscillator (MODOSC)
    • System Oscillator (SYSOSC)
  • Code Security Features
    • JTAG and SWD Lock
    • IP Protection (up to Four Secure Flash Zones, Each With Configurable Start Address and Size)
  • Enhanced System Features
    • Programmable Supervision and Monitoring of Supply Voltage
    • Multiple-Class Resets for Better Control of Application and Debug
    • 8-Channel DMA
    • RTC With Calendar and Alarm Functions
  • Timing and Control
    • Up to Four 16-Bit Timers, Each With up to Five Capture, Compare, PWM Capability
    • Two 32-Bit Timers, Each With Interrupt Generation Capability
  • Serial Communication
    • Up to Four eUSCI_A Modules
      • UART With Automatic Baud-Rate Detection
      • IrDA Encode and Decode
      • SPI (up to 16 Mbps)
    • Up to Four eUSCI_B Modules
      • I2C (With Multiple-Slave Addressing)
      • SPI (up to 16 Mbps)
  • Flexible I/O Features
    • Ultra-Low-Leakage I/Os (±20 nA Maximum)
    • All I/Os With Capacitive-Touch Capability
    • Up to 48 I/Os With Interrupt and Wake-up Capability
    • Up to 24 I/Os With Port Mapping Capability
    • Eight I/Os With Glitch Filtering Capability
  • Encryption and Data Integrity Accelerators
    • 128-, 192-, or 256-Bit AES Encryption and Decryption Accelerator
    • 32-Bit Hardware CRC Engine
  • JTAG and Debug Support
    • 4-Pin JTAG and 2-Pin SWD Debug Interfaces
    • Serial Wire Trace
    • Power Debug and Profiling of Applications

Applications

  • Industrial and Automation
    • Glass Breakage Detectors
    • Smart Thermostats
    • Access Panels
    • Gas Monitors
    • Field Transmitters
    • Process Automation
    • Home Automation
  • Metering
    • Flow Meters
    • Electric Meters
    • Communication Modules
  • Test and Measurement
    • Digital Multimeters
    • Wireless Digital Multimeters
    • Contactless and Hand-Held Digital Meters
  • Health and Fitness
    • Watches
    • Activity Monitors
    • Fitness Accessories
    • Blood Glucose Meters
  • Consumer Electronics
    • Mobile Devices
    • Sensor Hubs

Description

The SimpleLink MSP432P401x microcontrollers (MCUs) are optimized wireless host MCUs with an integrated 16-bit precision ADC, delivering ultra-low-power performance including 80 µA/MHz in active power and 660 nA in standby power with FPU and DSP extensions. As an optimized wireless host MCU, the MSP432P401x allows developers to add high-precision analog and memory extension to applications based on SimpleLink wireless connectivity solutions.

The MSP432P401x devices are part of the SimpleLink microcontroller (MCU) platform, which consists of Wi-Fi®, Bluetooth® low energy, Sub-1 GHz, and host MCUs. All share a common, easy-to-use development environment with a single core software development kit (SDK) and rich tool set. A one-time integration of the SimpleLink platform lets you add any combination of devices from the portfolio into your design. The ultimate goal of the SimpleLink platform is to achieve 100 percent code reuse when your design requirements change. For more information, visit www.ti.com/simplelink.

MSP432P401x devices are supported by a comprehensive ecosystem of tools, software, documentation, training, and support to get your development started quickly. The MSP-EXP432P401R LaunchPad development kit or MSP-TS432PZ100 target socket board (with additional MCU sample) along with the free SimpleLink MSP432 SDK is all you need to get started.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE(2)
MSP432P401RIPZ
MSP432P401MIPZ
LQFP (100)14 mm × 14 mm
MSP432P401RIZXH
MSP432P401MIZXH
NFBGA (80)5 mm × 5 mm
MSP432P401RIRGC
MSP432P401MIRGC
VQFN (64)9 mm × 9 mm
For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 9, or see the TI website.
The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 9.

Functional Block Diagram

Figure 1-1 shows the functional block diagram of the MSP432P401R and MSP432P401M devices.

MSP432P401R MSP432P401M functional_block_diagram_slas826.gif Figure 1-1 MSP432P401R, MSP432P401M Functional Block Diagram

The CPU and all of the peripherals in the device interact with each other through a common AHB matrix. In some cases, there are bridges between the AHB ports and the peripherals. These bridges are transparent to the application from a memory map perspective and, therefore, are not shown in the block diagram.