SLOS712I January 2011  – October 2016 OPA2836 , OPA836

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. OPA836-Related Devices
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information: OPA836
    5. 7.5Thermal Information: OPA2836
    6. 7.6Electrical Characteristics: VS = 2.7 V
    7. 7.7Electrical Characteristics: VS = 5 V
    8. 7.8Typical Characteristics
      1. 7.8.1Typical Characteristics: VS = 2.7 V
      2. 7.8.2Typical Performance Graphs: VS = 5 V
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagrams
    3. 8.3Feature Description
      1. 8.3.1Input Common-Mode Voltage Range
      2. 8.3.2Output Voltage Range
      3. 8.3.3Power-Down Operation
      4. 8.3.4Low-Power Applications and the Effects of Resistor Values on Bandwidth
      5. 8.3.5Driving Capacitive Loads
    4. 8.4Device Functional Modes
      1. 8.4.1Split-Supply Operation (±1.25 V to ±2.75 V)
      2. 8.4.2Single-Supply Operation (2.5 V to 5.5 V)
  9. Application and Implementation
    1. 9.1Application Information
      1. 9.1.1 Noninverting Amplifier
      2. 9.1.2 Inverting Amplifier
      3. 9.1.3 Instrumentation Amplifier
      4. 9.1.4 Attenuators
      5. 9.1.5 Single-Ended-to-Differential Amplifier
      6. 9.1.6 Differential-to-Signal-Ended Amplifier
      7. 9.1.7 Differential-to-Differential Amplifier
      8. 9.1.8 Gain Setting With OPA836 RUN Integrated Resistors
      9. 9.1.9 Pulse Application With Single-Supply
      10. 9.1.10ADC Driver Performance
    2. 9.2Typical Applications
      1. 9.2.1Audio Frequency Performance
        1. 9.2.1.1Design Requirements
        2. 9.2.1.2Detailed Design Procedure
        3. 9.2.1.3Application Curves
      2. 9.2.2Active Filters
        1. 9.2.2.1Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  12. 12Device and Documentation Support
    1. 12.1Device Support
      1. 12.1.1Development Support
      2. 12.1.2Related Documentation
    2. 12.2Related Links
    3. 12.3Receiving Notification of Documentation Updates
    4. 12.4Community Resources
    5. 12.5Trademarks
    6. 12.6Electrostatic Discharge Caution
    7. 12.7Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

Noninverting Amplifier

The OPA836 and OPA2836 devices can be used as noninverting amplifiers with signal input to the noninverting input, VIN+ . A basic block diagram of the circuit is shown in Figure 53.

If VIN = VREF + VSIG, then the output of the amplifier may be calculated according to Equation 1.

Equation 1. OPA836 OPA2836 EQ1_vout_los713.gif

The signal gain of the circuit is set by OPA836 OPA2836 Iline1_G_los713.gif, and VREF provides a reference around which the input and output signals swing. Output signals are in-phase with the input signals.

The OPA836 and OPA2836 devices are designed for the nominal value of RF to be 1 kΩ in gains other than +1. This gives excellent distortion performance, maximum bandwidth, best flatness, and best pulse response. RF = 1 kΩ must be used as a default unless other design goals require changing to other values. All test circuits used to collect data for this data sheet had RF = 1 kΩ for all gains other than +1. Gain of +1 is a special case where RF is shorted and RG is left open.

Inverting Amplifier

The OPA836 and OPA2836 devices can be used as inverting amplifiers with signal input to the inverting input, VIN– , through the gain setting resistor RG. A basic block diagram of the circuit is shown in Figure 54.

If VIN = VREF + VSIG, then the output of the amplifier may be calculated according to Equation 2.

Equation 2. OPA836 OPA2836 EQ2_vout2_los713.gif

The signal gain of the circuit is set by OPA836 OPA2836 Iline2_G2_los713.gif , and VREF provides a reference point around which the input and output signals swing. Output signals are 180° out-of-phase with the input signals. The nominal value of RF must be 1 kΩ for inverting gains.

Instrumentation Amplifier

Figure 64 is an instrumentation amplifier that combines the high input impedance of the differential-to-differential amplifier circuit and the common-mode rejection of the differential-to-single-ended amplifier circuit. This circuit is often used in applications where high input impedance is required (such as taps from a differential line) or in cases where the signal source has a high output impedance.

If VIN+ = VCM + VSIG+ and VIN– = VCM + VSIG– , then the output of the amplifier may be calculated according to Equation 3.

Equation 3. OPA836 OPA2836 EQ5_vout5_los713.gif

The signal gain of the circuit is set by OPA836 OPA2836 Iline5_G5_los713.gif. VCM is rejected, and VREF provides a level shift around which the output signal swings. The single-ended output signal is in-phase with the differential input signal.

OPA836 OPA2836 instru_amp_los712.gif Figure 64. Instrumentation Amplifier

Integrated solutions are available, but the OPA836 device provides a much lower-power, high-frequency solution. For best CMRR performance, resistors must be matched. A good guideline to follow is CMRR ≈ the resistor tolerance; so, 0.1% tolerance will provide approximately 60-dB CMRR.

Attenuators

The noninverting circuit of Figure 53 has minimum gain of 1. To implement attenuation, a resistor divider can be placed in series with the positive input, and the amplifier set for gain of 1 by shorting VOUT to VIN– and removing RG. Because the operational amplifier input is high impedance, the resistor divider sets the attenuation.

The inverting circuit of Figure 54 can be used as an attenuator by making RG larger than RF. The attenuation is the resistor ratio. For example, a 10:1 attenuator can be implemented with RF = 1 kΩ and RG = 10 kΩ.

Single-Ended-to-Differential Amplifier

Figure 65 shows an amplifier circuit that is used to convert single-ended signals to differential, and provides gain and level shifting. This circuit can be used for converting signals to differential in applications like line drivers for Cat5 cabling or driving differential-input SAR and ΔΣ ADCs.

With VIN = VREF + VSIG , the output of the amplifier may be calculated according to Equation 4.

Equation 4. OPA836 OPA2836 eq_single_ended_los712.gif

The differential-signal gain of the circuit is 2 × G, and VREF provides a reference around which the output signal swings. The differential output signal is in-phase with the single-ended input signal.

OPA836 OPA2836 single_ended_to_diff_los712.gif Figure 65. Single Ended to Differential Amplifier

Line termination on the output can be accomplished with resistors RO. The differential impedance seen from the line will be 2 × RO. For example, if 100-Ω Cat5 cable is used with double termination, the amplifier is typically set for a differential gain of 2 V/V (6 dB) with RF = 0 Ω (short), RG = open, 2R = 1 kΩ, R1 = 0 Ω, R = 499 Ω to balance the input bias currents, and RO = 49.9 Ω for output line termination. This configuration is shown in Figure 66.

For driving a differential-input ADC the situation is similar, but the output resistors, RO are selected with a capacitor across the ADC input for optimum filtering and settling-time performance.

OPA836 OPA2836 single_ended_to_diff_gain_los712.gif Figure 66. Cat5 Line Driver With Gain = 2 V/V (6 dB)

Differential-to-Signal-Ended Amplifier

Figure 67 shows a differential amplifier that is used to convert differential signals to single-ended and provides gain (or attenuation) and level shifting. This circuit can be used in applications like a line receiver for converting a differential signal from a Cat5 cable to a single-ended signal.

If VIN+ = VCM + VSIG+ and VIN– = VCM + VSIG– , then the output of the amplifier may be calculated according to Equation 5.

Equation 5. OPA836 OPA2836 EQ3_vout3_los713.gif

The signal gain of the circuit is OPA836 OPA2836 Iline3_G3_los713.gif , VCM is rejected, and VREF provides a level shift around which the output signal swings. The single ended output signal is in-phase with the differential input signal.

OPA836 OPA2836 dif_sng_amp_los712.gif Figure 67. Differential to Single-Ended Amplifier

Line termination can be accomplished by adding a shunt resistor across the VIN+ and VIN- inputs. The differential impedance is the shunt resistance in parallel with the input impedance of the amplifier circuit, which is usually much higher. For low gain and low line impedance, the resistor value to add is approximately the impedance of the line. For example if 100-Ω Cat5 cable is used with a gain of 1 amplifier and RF = RG = 1 kΩ, adding a 100-Ω shunt across the input will give a differential impedance of 98 Ω, which is adequate for most applications.

For best CMRR performance, resistors must be matched. Assuming CMRR ≈ the resistor tolerance, a 0.1% tolerance will provide about 60-dB CMRR.

Differential-to-Differential Amplifier

Figure 68 shows a differential amplifier that is used to amplify differential signals. This circuit has high input impedance and is used in differential line driver applications where the signal source is a high-impedance driver (for example, a differential DAC) that must drive a line.

If VIN± = VCM + VSIG± , then the output of the amplifier may be calculated according to Equation 6.

Equation 6. OPA836 OPA2836 EQ4_vout4_los713.gif

The signal gain of the circuit is set by OPA836 OPA2836 Iline4_G4_los713.gif , and VCM passes with unity gain. The amplifier in essence combines two noninverting amplifiers into one differential amplifier that shares the RG resistor, which makes RG effectively half its value when calculating the gain. The output signals are in-phase with the input signals.

OPA836 OPA2836 dif_dif_amp_los712.gif Figure 68. Differential to Differential Amplifier

Gain Setting With OPA836 RUN Integrated Resistors

The OPA836 RUN package option includes integrated gain-setting resistors for smallest possible footprint on a printed circuit board (≈ 2.00 mm × 2.00 mm). By adding circuit traces on the PCB, gains of +1, –1, –1.33, +2, +2.33, –3, +4, –4, +5, –5.33, +6.33, –7, +8 and inverting attenuations of –0.1429, –0.1875, –0.25, –0.33, –0.75 can be achieved.

Figure 69 shows a simplified view of how the OPA836IRUN integrated gain-setting network is implemented. Table 3 lists the required pin connections for various noninverting and inverting gains (reference Figure 53 and Figure 54). Table 4 shows the required pin connections for various attenuations using the inverting-amplifier architecture (reference Figure 54). Due to ESD protection devices being used on all pins, the absolute maximum and minimum input-voltage range, VS– – 0.7 V to VS+ + 0.7 V, applies to the gain-setting resistors, so attenuation of large input voltages requires external resistors to implement.

The gain-setting resistors are laser trimmed to 1% tolerance with nominal values of 1.6 kΩ, 1.2 kΩ, and 400 Ω. The gain-setting resistors have excellent temperature coefficients, and gain drift is superior to the drift with external gain-setting resistors. The 500-Ω and 1.5-pF capacitor in parallel with the 1.6-kΩ gain-setting resistor provide compensation for best stability and pulse response.

OPA836 OPA2836 OPA836IRUN_gain_los712.gif Figure 69. OPA836IRUN Gain-Setting Network

Table 3. Gain Settings

NONINVERTING GAIN
(Figure 53)
INVERTING GAIN
(Figure 54)
SHORT PINSSHORT PINSSHORT PINSSHORT PINS
1 V/V (0 dB)1 to 9
2 V/V (6.02 dB)–1 V/V (0 dB)1 to 92 to 86 to GND
2.33 V/V (7.36 dB)–1.33 V/V (2.5 dB)1 to 92 to 87 to GND
4 V/V (12.04 dB)–3 V/V (9.54 dB)1 to 82 to 76 to GND
5 V/V (13.98 dB)–4 V/V (12.04 dB)1 to 92 to 7 or 87 to 86 to GND
6.33 V/V (16.03 dB)–5.33 V/V (14.54 dB)1 to 92 to 6 or 86 to 87 to GND
8 V/V (18.06 dB)–7 V/V (16.90 dB)1 to 92 to 76 to GND

Table 4. Attenuator Settings

INVERTING GAIN
(Figure 54)
SHORT PINSSHORT PINSSHORT PINSSHORT PINS
–0.75 V/V (–2.5 dB)1 to 72 to 89 to GND
–0.333 V/V (–9.54 dB)1 to 62 to 78 to GND
–0.25 V/V (–12.04 dB)1 to 62 to 7 or 87 to 89 to GND
–0.1875 V/V (–14.54 dB)1 to 72 to 6 or 86 to 89 to GND
–0.1429 V/V (–16.90 dB)1 to 62 to 79 to GND

Pulse Application With Single-Supply

For pulsed applications, where the signal is at ground and pulses to a positive or negative voltage, the circuit bias-voltage considerations differ from those in an application with a signal that swings symmetrical about a reference point. Figure 70 shows a circuit where the signal is at ground (0 V) and pulses to a positive value.

OPA836 OPA2836 Ninv_sply_pulse_los1712.gif Figure 70. Noninverting Single Supply With Pulse

If the input signal pulses negative from ground, an inverting amplifier is more appropriate as shown in Figure 71. A key consideration in noninverting and inverting cases is that the input and output voltages are kept within the limits of the amplifier. Because the VICR of the OPA836 device includes the negative supply rail, the OPA836 operational amplifier is well-suited to this application.

OPA836 OPA2836 inv_sply_pulse_los712.gif Figure 71. Inverting Single Supply With Pulse

ADC Driver Performance

The OPA836 device provides excellent performance when driving high-performance delta-sigma (ΔΣ) and successive-approximation-register (SAR) ADCs in low-power audio and industrial applications.

To show achievable performance, the OPA836 device is tested as the drive amplifier for the ADS8326. The ADS8326 is a 16-bit, micro power, SAR ADC with pseudodifferential inputs and sample rates up to 250 kSPS. The device offers excellent noise and distortion performance in a small 8-pin SOIC or VSSOP (MSOP) package. Low power and small size make the ADS8326 and OPA836 devices an ideal solution for portable and battery-operated systems, remote data-acquisition modules, simultaneous multichannel systems, and isolated data acquisition.

With the circuit shown in Figure 72 to test the performance, Figure 73 shows the FFT plot with a 10-kHz input signal . The tabulated AC analysis is in Table 5.

OPA836 OPA2836 tst_cir_los712.gif Figure 72. OPA836 and ADS8326 Test Circuit
OPA836 OPA2836 FFT_los713.gif Figure 73. ADS8326 and OPA836 10-kHz FFT

Table 5. AC Analysis

TONE (Hz)SIGNAL (dBFS)SNR (dBc)THD (dBc)SINAD (dBc)SFDR (dBc)
10k–0.8583.3–86.681.6588.9

Typical Applications

Audio Frequency Performance

The OPA836 and OPA2836 devices provide excellent audio performance with low quiescent power. To show performance in the audio band, an audio analyzer from Audio Precision (2700 series) tests THD+N and FFT at 1 VRMS output voltage.

Figure 74 shows the circuit used for the audio-frequency performance test.

OPA836 OPA2836 AP_tst_cir_los712.gif
The 100-pF capacitor to ground on the input helped to decouple noise pick up in the lab and improved noise performance.
Figure 74. OPA836 Audio Precision Analyzer Test Circuit

Design Requirements

Design a low distortion, single-ended input to single-ended output audio amplifier using the OPA836 device. The 2700-series audio analyzer from Audio Precision is used as the signal source and also as the measurement system.

Table 6. Design Requirements

CONFIGURATIONINPUT
EXCITATION
PERFORMANCE
TARGET
RLoad
OPA836 Unity Gain Config.1 KHz Tone Frequency >110 dBc SFDR 300 Ω and
100 kΩ

Detailed Design Procedure

The OPA836 device is tested in this application in a unity-gain buffer configuration. A buffer configuration is selected for maximum loop gain of the amplifier circuit. At higher closed-loop gains, the loop gain of the circuit reduces, which increases the harmonic distortion. The relationship between distortion and closed-loop gain at a fixed input frequency is shown in Figure 36 in Typical Performance Graphs: VS = 5 V. The test was performed under using resistive loads of 300 Ω and 100 KΩ. Figure 34 shows the distortion performance of the amplifier versus the resistive load. Output loading, output swing, and closed-loop gain play a key role in determining the distortion performance of the amplifier.

NOTE

The 100-pF capacitor to ground on the input helped to decouple noise pickup in the lab and improved noise performance.

The Audio Precision was configured as a single-ended output in this application circuit. In applications where a differential output is available, the OPA836 device can be configured as a differential-to-single-ended amplifier as shown in Figure 67. Power-supply bypassing is critical to reject noise from the power supplies. A 2.2-μF supply decoupling capacitor must be placed within 2 inches of the device and can be shared with other operational amplifiers on the same board. A 0.1-μF supply decoupling capacitor must be placed as close to the supply pins as possible, preferably within 0.1 inch. For a split supply, a capacitor is required for both supplies. A 0.1-µF capacitor placed directly between the supplies is also beneficial for improving system noise performance. If the output load is heavy, such as 16 Ω to 32 Ω, performance of the amplifier could begin to degrade. To drive such heavy loads, both channels of the OPA2836 device can be paralleled with their outputs isolated with 1-Ω resistors to reduce the loading effects.

Application Curves

Figure 75 shows the THD+N performance with 100-kΩ and 300-Ω loads, and with A-weighting and with no weighting. Both loads show similar performance. With no weighting, the THD+N performance is dominated by the noise for both loads. A-weighting provides filtering that improves the noise, revealing the increased distortion with RL = 300 Ω.

Figure 76 and Figure 77 show the FFT output with a 1-kHz tone and 100-kΩ and 300-Ω loads. To show relative performance of the device versus the test set, one channel has the OPA836 device in-line between the generator output and the analyzer. The other channel is in “Gen Mon” loopback mode, which internally connects the signal generator to the analyzer input. With 100-kΩ load, Figure 76, the curves are indistinguishable from each other except for noise, which means the OPA836 device cannot be directly measured. With 300-Ω load, as shown in Figure 77, the main difference between the curves is that the OPA836 device shows slightly higher even-order harmonics, but the performance of the test set masks the odd-order harmonics.

OPA836 OPA2836 app_tc3_5v_los712.gif Figure 75. OPA836 1 VRMS 20-Hz to 80-kHz THD+N
OPA836 OPA2836 app_FFT2_los712.gif Figure 77. OPA836 and AP Gen Mon 10-kHz FFT Plot;
VOUT = 1 VRMS, RL = 300 Ω
OPA836 OPA2836 app_FFT1_los712.gif Figure 76. OPA836 and AP Gen Mon 10-kHz FFT Plot; VOUT = 1 VRMS, RL = 100 kΩ

Active Filters

The OPA836 and OPA2836 devices are good choices for active filters. Figure 78 and Figure 79 show MFB and Sallen-Key circuits designed using the WEBENCH® Filter Designer to implement second-order low-pass Butterworth filter circuits. Figure 80 shows the frequency response.

Other MFB and Sallen-Key filter circuits offer similar performance. The main difference is the MFB is an inverting amplifier in the pass-band and the Sallen-Key is noninverting. The primary advantage for each is the Sallen-Key in unity gain has no resistor gain-error term, and thus no sensitivity to gain error, while the MFB has better attenuation properties beyond the bandwidth of the operational amplifier.

OPA836 OPA2836 MFB_cir_los712.gif Figure 78. MFB 100-kHz Second-Order Low-Pass Butterworth Filter Circuit
OPA836 OPA2836 sllen_key_los712.gif Figure 79. Sallen-Key 100-kHz Second-Order Low-Pass Butterworth Filter Circuit

Application Curve

OPA836 OPA2836 app_tc2_5v_los713.gif Figure 80. MFB and Sallen-Key Second Order Low-Pass Butterworth Filter Response