SLOS712I January 2011  – October 2016 OPA2836 , OPA836

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. OPA836-Related Devices
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information: OPA836
    5. 7.5Thermal Information: OPA2836
    6. 7.6Electrical Characteristics: VS = 2.7 V
    7. 7.7Electrical Characteristics: VS = 5 V
    8. 7.8Typical Characteristics
      1. 7.8.1Typical Characteristics: VS = 2.7 V
      2. 7.8.2Typical Performance Graphs: VS = 5 V
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagrams
    3. 8.3Feature Description
      1. 8.3.1Input Common-Mode Voltage Range
      2. 8.3.2Output Voltage Range
      3. 8.3.3Power-Down Operation
      4. 8.3.4Low-Power Applications and the Effects of Resistor Values on Bandwidth
      5. 8.3.5Driving Capacitive Loads
    4. 8.4Device Functional Modes
      1. 8.4.1Split-Supply Operation (±1.25 V to ±2.75 V)
      2. 8.4.2Single-Supply Operation (2.5 V to 5.5 V)
  9. Application and Implementation
    1. 9.1Application Information
      1. 9.1.1 Noninverting Amplifier
      2. 9.1.2 Inverting Amplifier
      3. 9.1.3 Instrumentation Amplifier
      4. 9.1.4 Attenuators
      5. 9.1.5 Single-Ended-to-Differential Amplifier
      6. 9.1.6 Differential-to-Signal-Ended Amplifier
      7. 9.1.7 Differential-to-Differential Amplifier
      8. 9.1.8 Gain Setting With OPA836 RUN Integrated Resistors
      9. 9.1.9 Pulse Application With Single-Supply
      10. 9.1.10ADC Driver Performance
    2. 9.2Typical Applications
      1. 9.2.1Audio Frequency Performance
        1. 9.2.1.1Design Requirements
        2. 9.2.1.2Detailed Design Procedure
        3. 9.2.1.3Application Curves
      2. 9.2.2Active Filters
        1. 9.2.2.1Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  12. 12Device and Documentation Support
    1. 12.1Device Support
      1. 12.1.1Development Support
      2. 12.1.2Related Documentation
    2. 12.2Related Links
    3. 12.3Receiving Notification of Documentation Updates
    4. 12.4Community Resources
    5. 12.5Trademarks
    6. 12.6Electrostatic Discharge Caution
    7. 12.7Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Detailed Description

Overview

The OPAx836 family of bipolar-input operational amplifiers offers excellent bandwidth of 205 MHz with ultra-low THD of 0.00003% at 1 kHz. The OPAx836 device can swing to within 200 mV of the supply rails while driving a 1-kΩ load. The input common-mode of the amplifier can swing to 200 mV below the negative supply rail. This level of performance is achieved at 1 mA of quiescent current per amplifier channel.

Functional Block Diagrams

OPA836 OPA2836 non_inv_amp_los712.gif Figure 53. Noninverting Amplifier
OPA836 OPA2836 inv_amp_los712.gif Figure 54. Inverting Amplifier

Feature Description

Input Common-Mode Voltage Range

When the primary design goal is a linear amplifier with high CMRR, it is important to not violate the input common-mode voltage range (VICR) of an operational amplifier.

The common-mode input range specifications in the table data use CMRR to set the limit. The limits are selected to ensure CMRR will not degrade more than 3 dB below the CMRR limit if the input voltage is kept within the specified range. The limits cover all process variations and most parts will be better than specified. The typical specifications are from 0.2 V below the negative rail to 1.1 V below the positive rail.

Assuming the operational amplifier is in linear operation, the voltage difference between the input pins is small (ideally 0 V) and input common-mode voltage is analyzed at either input pin with the other input pin assumed to be at the same potential. The voltage at VIN+ is simple to evaluate. In noninverting configuration, Figure 53, the input signal, VIN, must not violate the VICR. In inverting configuration, Figure 54, the reference voltage, VREF, must be within the VICR.

The input voltage limits have fixed headroom to the power rails and track the power supply voltages. For one 5-V supply, the linear input voltage ranges from –0.2 V to 3.9 V and from –0.2 V to 1.6 V for a 2.7-V supply. The delta headroom from each power supply rail is the same in either case: –0.2 V and 1.1 V.

Output Voltage Range

The OPA836 and OPA2836 devices are rail-to-rail output (RRO) operational amplifiers. Rail-to-rail output typically means the output voltage swings within a couple hundred millivolts of the supply rails. There are different ways to specify this: one is with the output still in linear operation and another is with the output saturated. Saturated output voltages are closer to the power supply rails than linear outputs, but the signal is not a linear representation of the input. Linear output is a better representation of how well a device performs when used as a linear amplifier. Saturation and linear operation limits are affected by the output current, where higher currents lead to more loss in the output transistors.

Figure 11 and Figure 37 show saturated voltage-swing limits versus output load resistance and Figure 12 and Figure 38 show the output saturation voltage versus load current. Given a light load, the output voltage limits have nearly constant headroom to the power rails and track the power supply voltages. For example, with a 2-kΩ load and single 5-V supply, the linear output voltage ranges from 0.15 V to 4.8 V, and ranges from 0.15 V to 2.5 V for a 2.7-V supply. The delta from each power supply rail is the same in either case: 0.15 V and 0.2 V.

With devices like the OPA836 and OPA2836, where the input range is lower than the output range, typically the input will limit the available signal swing only in noninverting gain of 1. Signal swing in noninverting configurations in gains > +1 and inverting configurations in any gain is typically limited by the output voltage limits of the operational amplifier.

Power-Down Operation

The OPA836 and OPA2836 devices include a power-down mode. Under logic control, the amplifiers can switch from normal operation to a standby current of < 1.5 µA. When the PD pin is connected high, the amplifier is active. Connecting PD pin low disables the amplifier and places the output in a high-impedance state. When the amplifier is configured as a unity-gain buffer, the output stage is in a high dc-impedance state. To protect the input stage of the amplifier, the devices use internal, back-to-back ESD diodes between the inverting and noninverting input pins. This configuration creates a parallel low-impedance path from the amplifier output to the noninverting pin when the differential voltage between the pins exceeds a diode voltage drop. When the op amp is configured in other gains, the feedback (RF) and gain (RG) resistor network forms a parallel load.

The PD pin must be actively driven high or low and must not be left floating. If the power-down mode is not used, PD must be tied to the positive supply rail.

PD logic states are TTL with reference to the negative supply rail and VS–. When the operational amplifier is powered from single-supply and ground and driven from logic devices with similar VDD, voltages to the operational amplifier do not require any special consideration. When the operational amplifier is powered from a split supply, with VS– below ground, an open-collector type of interface with pullup resistor is more appropriate. Pullup resistor values must be lower than 100 kΩ. Additionally, the drive logic must be negated due to the inverting action of an open-collector gate.

Low-Power Applications and the Effects of Resistor Values on Bandwidth

The OPA836 and OPA2836 devices are designed for the nominal value of RF to be 1 kΩ in gains other than +1. This gives excellent distortion performance, maximum bandwidth, best flatness, and best pulse response, but it also loads the amplifier. For example; in gain of 2 with RF = RG = 1 kΩ, RG to ground, and VOUT = 4 V, 2 mA of current will flow through the feedback path to ground. In gain of +1, RG is open and no current will flow to ground. In low-power applications, it is desirable to reduce the current in the feedback by increasing the gain-setting resistors values. Using larger value gain resistors has two primary side effects (other than lower power) due to their interaction with parasitic circuit capacitance:

  • Lowers the bandwidth
  • Lowers the phase margin
    • This causes peaking in the frequency response
    • This also causes overshoot and ringing in the pulse response

Figure 55 shows the small-signal frequency response on OPA836EVM for noninverting gain of 2 with RF and RG equal to 1 kΩ, 10 kΩ, and 100 kΩ. The test was done with RL = 1 kΩ. Due to loading effects of RL, lower RL values may reduce the peaking, but higher values will not have a significant effect.

OPA836 OPA2836 app_tc1_5v_los712.gif Figure 55. Frequency Response With Various Gain-Setting Resistor Values

As expected, larger value gain resistors cause lower bandwidth and peaking in the response (peaking in the frequency response is synonymous with overshoot and ringing in the pulse response). Adding 1-pF capacitors in parallel with RF helps compensate the phase margin and restores flat frequency response. Figure 56 shows the test circuit.

OPA836 OPA2836 tst2_cir_los712.gif Figure 56. G = 2 Test Circuit for Various Gain-Setting Resistor Values

Driving Capacitive Loads

The OPA836 and OPA2836 devices can drive up to a nominal capacitive load of 2.2 pF on the output with no special consideration. When driving capacitive loads greater than 2.2 pF, TI recommends using a small resister (RO) in series with the output as close to the device as possible. Without RO, capacitance on the output interacts with the output impedance of the amplifier causing phase shift in the loop gain of the amplifier that will reduce the phase margin. This will cause peaking in the frequency response and overshoot and ringing in the pulse response. Interaction with other parasitic elements may lead to instability or oscillation. Inserting RO will isolate the phase shift from the feedback path and restore the phase margin; however, RO can limit the bandwidth slightly.

Figure 57 shows the test circuit and Figure 43 shows the recommended values of RO versus capacitive loads, CL. See Figure 40 for the frequency response with various values.

OPA836 OPA2836 RO_CL_tst_cir_los712.gif Figure 57. RO versus CL Test Circuit

Device Functional Modes

Split-Supply Operation (±1.25 V to ±2.75 V)

To facilitate testing with common lab equipment, the OPA836 EVM (see OPA835DBV, OPA836DBV EVM, SLOU314) is built to allow for split-supply operation. This configuration eases lab testing because the mid-point between the power rails is ground, and most signal generators, network analyzers, oscilloscopes, spectrum analyzers and other lab equipment have inputs and outputs with a ground reference.

Figure 58 shows a simple noninverting configuration analogous to Figure 53 with ±2.5-V supply and VREF equal to ground. The input and output will swing symmetrically around ground. For ease of use, split supplies are preferred in systems where signals swing around ground.

OPA836 OPA2836 simp_conf_los712.gif Figure 58. Split-Supply Operation

Single-Supply Operation (2.5 V to 5.5 V)

Often, newer systems use a single power supply to improve efficiency and reduce the cost of the power supply. The OPA836 and OPA2836 devices are designed for use with a single supply with no change in performance compared to a split supply, as long as the input and output are biased within the linear operation of the device.

To change the circuit from split supply to single supply, level shift of all voltages by half the difference between the power supply rails. For example, changing from ±2.5-V split supply to 5-V single supply is shown in Figure 59.

OPA836 OPA2836 sin_sply_los712.gif Figure 59. Single-Supply Concept

A practical circuit will have an amplifier or other circuit providing the bias voltage for the input, and the output of this amplifier stage provides the bias for the next stage.

Figure 60 shows a typical noninverting amplifiercircuit. With 5-V single-supply, a mid-supply reference generator is needed to bias the negative side through RG. To cancel the voltage offset that would otherwise be caused by the input bias currents, R1 is selected to be equal to RF in parallel with RG. For example, if gain of 2 is required and RF = 1 kΩ, select RG = 1 kΩ to set the gain and R1 = 499 Ω for bias-current cancellation. The value for C depends on the reference; TI recommends a value of at least 0.1 µF to limit noise.

OPA836 OPA2836 sin_sply_wref_los712.gif Figure 60. Noninverting Single Supply With Reference

Figure 61 shows a similar noninverting single-supply scenario with the reference generator replaced by the Thevenin equivalent using resistors and the positive supply. RG’ and RG” form a resistor divider from the 5-V supply and are used to bias the negative side with their parallel sum equal to the equivalent RG to set the gain. To cancel the voltage offset that would otherwise be caused by the input bias currents, R1 is selected to be equal to RF in parallel with RG’ in parallel with RG” (R1= RF || RG’ || RG”). For example, if gain of 2 is required and RF = 1 kΩ, selecting RG’ = RG” = 2 kΩ gives equivalent parallel sum of 1 kΩ, sets the gain to 2, and references the input to mid supply (2.5 V). R1 is then set to 499 Ω for bias-current cancellation. The resistor divider costs less than the 2.5 V reference in Figure 60 but may increase the current from the 5-V supply.

OPA836 OPA2836 non_inv_wris_los712.gif Figure 61. Noninverting Single Supply With Resistors

Figure 62 shows a typical inverting amplifier situation. With 5-V single supply, a mid-supply reference generator is needed to bias the positive side through R1. To cancel the voltage offset that would otherwise be caused by the input bias currents, R1 is selected to be equal to RF in parallel with RG. For example if gain of –2 is required and RF = 1 kΩ, select RG = 499 Ω to set the gain and R1 = 332 Ω for bias-current cancellation. The value for C is dependent on the reference, but TI recommends a value of at least 0.1 µF to limit noise into the operational amplifier.

OPA836 OPA2836 inv_sply_Wref_los712.gif Figure 62. Inverting Single Supply With Reference

Figure 63 shows a similar inverting single-supply scenario with the reference generator replaced by the Thevenin equivalent using resistors and the positive supply. R1 and R2 form a resistor divider from the 5-V supply and are used to bias the positive side. To cancel the voltage offset that would otherwise be caused by the input bias currents, set the parallel sum of R1 and R2 equal to the parallel sum of RF and RG. C must be added to limit coupling of noise into the positive input. For example if gain of –2 is required and RF = 1 kΩ, select RG = 499 Ω to set the gain. R1 = R2 = 665 Ω for mid-supply voltage bias and for operational amplifier input bias-current cancellation. A good value for C is 0.1 µF. The resistor divider costs less than the 2.5-V reference in Figure 62 but may increase the current from the 5-V supply.

OPA836 OPA2836 inv_sply_Wres_los712.gif Figure 63. Inverting Single Supply With Resistors