SLOS712I January 2011  – October 2016 OPA2836 , OPA836

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. OPA836-Related Devices
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information: OPA836
    5. 7.5Thermal Information: OPA2836
    6. 7.6Electrical Characteristics: VS = 2.7 V
    7. 7.7Electrical Characteristics: VS = 5 V
    8. 7.8Typical Characteristics
      1. 7.8.1Typical Characteristics: VS = 2.7 V
      2. 7.8.2Typical Performance Graphs: VS = 5 V
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagrams
    3. 8.3Feature Description
      1. 8.3.1Input Common-Mode Voltage Range
      2. 8.3.2Output Voltage Range
      3. 8.3.3Power-Down Operation
      4. 8.3.4Low-Power Applications and the Effects of Resistor Values on Bandwidth
      5. 8.3.5Driving Capacitive Loads
    4. 8.4Device Functional Modes
      1. 8.4.1Split-Supply Operation (±1.25 V to ±2.75 V)
      2. 8.4.2Single-Supply Operation (2.5 V to 5.5 V)
  9. Application and Implementation
    1. 9.1Application Information
      1. 9.1.1 Noninverting Amplifier
      2. 9.1.2 Inverting Amplifier
      3. 9.1.3 Instrumentation Amplifier
      4. 9.1.4 Attenuators
      5. 9.1.5 Single-Ended-to-Differential Amplifier
      6. 9.1.6 Differential-to-Signal-Ended Amplifier
      7. 9.1.7 Differential-to-Differential Amplifier
      8. 9.1.8 Gain Setting With OPA836 RUN Integrated Resistors
      9. 9.1.9 Pulse Application With Single-Supply
      10. 9.1.10ADC Driver Performance
    2. 9.2Typical Applications
      1. 9.2.1Audio Frequency Performance
        1. 9.2.1.1Design Requirements
        2. 9.2.1.2Detailed Design Procedure
        3. 9.2.1.3Application Curves
      2. 9.2.2Active Filters
        1. 9.2.2.1Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  12. 12Device and Documentation Support
    1. 12.1Device Support
      1. 12.1.1Development Support
      2. 12.1.2Related Documentation
    2. 12.2Related Links
    3. 12.3Receiving Notification of Documentation Updates
    4. 12.4Community Resources
    5. 12.5Trademarks
    6. 12.6Electrostatic Discharge Caution
    7. 12.7Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Layout

Layout Guidelines

The OPA835DBV, OPA836DBV EVM (SLOU314) can be used as a reference when designing the circuit board. TI recommends following the EVM layout of the external components near the amplifier, ground-plane construction, and power routing. General guidelines are listed as follows:

  1. Signal routing must be direct and as short as possible into and out of the operational amplifier.
  2. The feedback path must be short and direct avoiding vias if possible especially with G = +1.
  3. Ground or power planes must be removed from directly under the negative input and output pins of the amplifier.
  4. TI recommends placing a series output resistor as close to the output pin as possible. See Series Output Resistor vs Capacitive Load (Figure 17) for recommended values for the expected capacitive load.
  5. A 2.2-µF power-supply decoupling capacitor must be placed within two inches of the device and can be shared with other operational amplifiers. For spit supply, a capacitor is required for both supplies.
  6. A 0.1-µF power-supply decoupling capacitor must be placed as close to the power supply pins as possible, preferably within 0.1 inch. For split supply, a capacitor is required for both supplies.
  7. The PD pin uses TTL logic levels. If the pin is not used, it must be tied to the positive supply to enable the amplifier. If the pin is used, it must be actively driven. A bypass capacitor is not necessary, but is used for robustness in noisy environments.

Layout Example

OPA836 OPA2836 layoutexample1.png Figure 81. Top Layer
OPA836 OPA2836 layoutexample2.png Figure 82. Bottom Layer