SBOS745A May 2016  – June 2016 OPT3002

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6Timing Requirements
    7. 6.7Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1Automatic Full-Scale Range Setting
      2. 7.3.2Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
      3. 7.3.3I2C Bus Overview
        1. 7.3.3.1Serial Bus Address
        2. 7.3.3.2Serial Interface
    4. 7.4Device Functional Modes
      1. 7.4.1Automatic Full-Scale Setting Mode
      2. 7.4.2Interrupt Reporting Mechanism Modes
        1. 7.4.2.1Latched Window-Style Comparison Mode
        2. 7.4.2.2Transparent Hysteresis-Style Comparison Mode
        3. 7.4.2.3End-of-Conversion Mode
        4. 7.4.2.4End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
    5. 7.5Programming
      1. 7.5.1Writing and Reading
        1. 7.5.1.1High-Speed I2C Mode
        2. 7.5.1.2General-Call Reset Command
        3. 7.5.1.3SMBus Alert Response
    6. 7.6Register Maps
      1. 7.6.1Internal Registers
        1. 7.6.1.1Register Descriptions
          1. 7.6.1.1.1Result Register (address = 00h)
          2. 7.6.1.1.2Configuration Register (address = 01h) [reset = C810h]
          3. 7.6.1.1.3Low-Limit Register (address = 02h) [reset = C0000h]
          4. 7.6.1.1.4High-Limit Register (address = 03h) [reset = BFFFh]
          5. 7.6.1.1.5Manufacturer ID Register (address = 7Eh) [reset = 5449h]
  8. Application and Implementation
    1. 8.1Application Information
      1. 8.1.1Electrical Interface
      2. 8.1.2Optical Interface
      3. 8.1.3Compensation for the Spectral Response
    2. 8.2Do's and Don'ts
  9. Power-Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Documentation Support
      1. 11.1.1Related Documentation
    2. 11.2Receiving Notification of Documentation Updates
    3. 11.3Community Resources
    4. 11.4Trademarks
    5. 11.5Electrostatic Discharge Caution
    6. 11.6Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1Soldering and Handling Recommendations
    2. 12.2DNP (S-PDSO-N6) Mechanical Drawings

Detailed Description

Overview

The OPT3002 measures the light that illuminates the device within the device spectral range of 300 nm to 1000 nm.

The OPT3002 is fully self-contained to measure the ambient light and report the result digitally over the I2C bus. The result can also be used to alert a system and interrupt a processor with the INT pin. The result can also be summarized with a programmable window comparison and communicated with the INT pin.

The OPT3002 can be configured into an automatic full-scale, range-setting mode that always selects the optimal full-scale range setting for the lighting conditions. This mode automatically selects the optimal full-scale range for the given lighting condition, thus eliminating the requirement of programming many measurement and readjustment cycles of the full-scale range. The device can operate continuously or in single-shot measurement modes.

The device integrates its result over either 100 ms or 800 ms, so the effects of 50-Hz and 60-Hz noise sources from typical light bulbs are nominally reduced to a minimum.

The device starts up in a low-power shutdown state, such that the OPT3002 only consumes active-operation power after being programmed into an active state.

Functional Block Diagram

OPT3002 ai_block_diag_sbos745.gif

Feature Description

Automatic Full-Scale Range Setting

The OPT3002 has an automatic full-scale range setting feature that eliminates the need to predict and set the optimal range for the device. In this mode, the OPT3002 automatically selects the optimal full-scale range for the given lighting condition. The OPT3002 has a high degree of result matching between the full-scale range settings. This matching eliminates the problem of varying results or the need for range-specific, user-calibrated gain factors when different full-scale ranges are chosen. For further details, see the Automatic Full-Scale Setting Mode section.

Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms

The device has an interrupt reporting system that allows the processor connected to the I2C bus to go to sleep, or otherwise ignore the device results, until a user-defined event occurs that requires possible action. Alternatively, this same mechanism can also be used with any system that can take advantage of a single digital signal that indicates whether the light is above or below the levels of interest.

The interrupt event conditions are controlled by the high-limit and low-limit registers, as well as the configuration register latch and fault count fields. The results of comparing the result register with the high-limit register and low-limit register are referred to as fault events. The fault count field (configuration register, bits FC[1:0]) dictates how many consecutive same-result fault events are required to trigger an interrupt event and subsequently change the state of the interrupt reporting mechanisms (that is, the INT pin, the flag high field, and the flag low field). The latch field allows a choice between a latched window-style comparison and a transparent hysteresis-style comparison.

The INT pin has an open-drain output that requires the use of a pullup resistor. This open-drain output allows multiple devices with open-drain INT pins to be connected to the same line, thus creating a logical NOR or AND function between the devices. The polarity of the INT pin can be controlled with the polarity of the interrupt field in the configuration register. When the POL field is set to 0, the pin operates in an active low behavior that pulls the pin low when the INT pin becomes active. When the POL field is set to 1, the pin operates in an active high behavior and becomes high impedance, thus allowing the pin to go high when the INT pin becomes active.

Additional details of the interrupt reporting registers are described in the Interrupt Reporting Mechanism Modes and Internal Registers sections.

I2C Bus Overview

The OPT3002 offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are essentially compatible with one another. The I2C interface is used throughout this document as the primary example with the SMBus protocol specified only when a difference between the two protocols is discussed.

The OPT3002 is connected to the bus with two pins: an SCL clock input pin and an SDA open-drain bidirectional data pin. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates start and stop conditions. To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from a high logic level to a low logic level when SCL is high. All slaves on the bus shift in the slave address byte on the SCL rising edge, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an acknowledge bit by pulling SDA low.

Data transfer is then initiated and eight bits of data are sent, followed by an acknowledge bit. During data transfer, SDA must remain stable when SCL is high. Any change in SDA when SCL is high is interpreted as a start or stop condition. When all data are transferred, the master generates a stop condition, as indicated by pulling SDA from low to high when SCL is high. The OPT3002 includes a 28-ms timeout on the I2C interface to prevent locking up the bus. If the SCL line is held low for this duration of time, then the bus state machine is reset.

Serial Bus Address

To communicate with the OPT3002, the master must first initiate an I2C start command. Then, the master must address slave devices via a slave address byte. The slave address byte consists of seven address bits and a direction bit that indicates whether the action is to be a read or write operation.

Four I2C addresses are possible by connecting the ADDR pin to one of four pins: GND, VDD, SDA, or SCL. Table 1 summarizes the possible addresses with the corresponding ADDR pin configuration. The state of the ADDR pin is sampled on every bus communication and must be driven or connected to the desired level before any activity on the interface occurs.

Table 1. Possible I2C Addresses with the Corresponding ADDR Configuration

DEVICE I2C ADDRESSADDR PIN
1000100GND
1000101VDD
1000110SDA
1000111SCL

Serial Interface

The OPT3002 operates as a slave device on both the I2C bus and SMBus. Connections to the bus are made via the SCL clock input line and the SDA open-drain I/O line. The OPT3002 supports the transmission protocol for standard mode (up to 100 kHz), fast mode (up to 400 kHz), and high-speed mode (up to 2.6 MHz). All data bytes are transmitted most-significant bits first.

The SDA and SCL pins feature integrated spike-suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. See the Electrical Interface section for further details of the I2C bus noise immunity.

Device Functional Modes

Automatic Full-Scale Setting Mode

The OPT3002 has an automatic full-scale-range setting mode that eliminates the need for a user to predict and set the optimal range for the device. This mode is entered when the configuration register range number field (RN[3:0]) is set to 1100b.

The first measurement that the device takes in auto-range mode is a 10-ms range assessment measurement. The device then determines the appropriate full-scale range to take its first full measurement.

For subsequent measurements, the full-scale range is set by the result of the previous measurement. If a measurement is towards the low side of full-scale, then the full-scale range is decreased by one or two settings for the next measurement. If a measurement is towards the upper side of full-scale, then the full-scale range is increased by one setting for the next measurement.

If the measurement exceeds the full-scale range, resulting from a fast-increasing optical transient event, then the current measurement is aborted. This invalid measurement is not reported. A 10-ms measurement is taken to assess and properly reset the full-scale range. Then, a new measurement is taken with this proper full-scale range. Therefore, during a fast-increasing optical transient in this mode, a measurement can possibly take longer to complete and report than indicated by the configuration register conversion time field (CT).

Interrupt Reporting Mechanism Modes

There are two major types of interrupt reporting mechanism modes: latched window-style comparison mode and transparent hysteresis-style comparison mode. The configuration register latch field (L) (see the configuration register, bit 4) controls which of these two modes is used. An end-of-conversion mode is also associated with each major mode type. The end-of-conversion mode is active when the two most significant bits of the threshold low register are set to 11b. The mechanisms report via the flag high and flag low fields, the conversion ready field, and the INT pin.

Latched Window-Style Comparison Mode

The latched window-style comparison mode is typically selected when using the OPT3002 to interrupt an external processor. In this mode, a fault is recognized when the input signal is above the high-limit register or below the low-limit register. When the consecutive fault events trigger the interrupt reporting mechanisms, these mechanisms are latched, thus reporting whether the fault is the result of a high or low comparison. These mechanisms remain latched until the configuration register is read, which clears the INT pin and flag high and flag low fields. The SMBus alert response protocol, described in detail in the SMBus Alert Response section, clears the pin but does not clear the flag high and flag low fields. The behavior of this mode, along with the conversion ready flag, is summarized in Table 2. Note that Table 2 does not apply when the two threshold low register MSBs (see the Transparent Hysteresis-Style Comparison Mode section for clarification on the MSBs) are set to 11b.

Table 2. Latched Window-Style Comparison Mode: Flag Setting and Clearing Summary(2)(4)

OPERATIONFLAG HIGH FIELDFLAG LOW FIELDINT PIN(1)CONVERSION READY FIELD
The result register is above the high-limit register for fault count times; see the result register and the high-limit register for further details.1XActive1
The result register is below the low-limit register for fault count times; see the result register and the low-limit register for further details.X1Active1
The conversion is complete with fault count criterion not metXXX1
Configuration register read(3)00Inactive0
Configuration register write, M[1:0] = 00b (shutdown)XXXX
Configuration register write, M[1:0] > 00b (not shutdown)XXX0
SMBus alert response protocolXXInactiveX
The INT pin depends on the setting of the polarity field (POL). The INT pin is low when the pin state is active and POL = 0 (active low) or when the pin state is inactive and POL = 1 (active high).
X = no change from the previous state.
Immediately after the configuration register is read, the device automatically resets the conversion ready field to its 0 state. Thus, if two configuration register reads are performed immediately after a conversion completion, the first reads 1 and the second reads 0.
The high-limit register is assumed to be greater than the low-limit register. If this assumption is incorrect, the flag high field and flag low field can take on different behaviors.

Transparent Hysteresis-Style Comparison Mode

The transparent hysteresis-style comparison mode is typically used when a single digital signal is desired that indicates whether the input light is higher than or lower than a light level of interest. If the result register is higher than the high-limit register for a consecutive number of events set by the fault count field, then the INT line is set to active, the flag high field is set to 1, and the flag low field is set to 0. If the result register is lower than the low-limit register for a consecutive number of events set by the fault count field, then the INT line is set to inactive, the flag low field is set to 1, and the flag high field is set to 0. The INT pin and flag high and flag low fields do not change state with configuration reads and writes. The INT pin and flag fields continually report the appropriate comparison of the light to the low-limit and high-limit registers. The device does not respond to the SMBus alert response protocol when in either of the two transparent comparison modes (configuration register, latch field = 0). The behavior of this mode, along with the conversion ready is summarized in Table 3. Note that Table 3 does not apply when the two threshold low register MSBs (LE[3:2] from Table 11) are set to 11.

Table 3. Transparent Hysteresis-Style Comparison Mode: Flag Setting and Clearing Summary(2)(4)

OPERATIONFLAG HIGH FIELDFLAG LOW FIELDINT PIN(1)CONVERSION READY FIELD
The result register is above the high-limit register for fault count times; see the result register and the high-limit register for further details.10Active1
The result register is below the low-limit register for fault count times; see the result register and the low-limit register for further details.01Inactive1
The conversion is complete with fault count criterion not metXXX1
Configuration register read(3)XXX0
Configuration register write, M[1:0] = 00b (shutdown)XXXX
Configuration register write, M[1:0] > 00b (not shutdown)XXX0
SMBus alert response protocolXXXX

End-of-Conversion Mode

An end-of-conversion indicator mode can be used when every measurement is desired to be read by the processor, prompted by the INT pin going active on every measurement completion. This mode is entered by setting the most significant two bits of the low-limit register (LE[3:2] from the low-limit register) to 11b. This end-of-conversion mode is typically used in conjunction with the latched window-style comparison mode. The INT pin becomes inactive when the configuration register is read or the configuration register is written with a non-shutdown parameter or in response to an SMBus alert response. Table 4 summarizes the interrupt reporting mechanisms as a result of various operations.

Table 4. End-of-Conversion Mode When in Latched Window-Style Comparison Mode:
Flag Setting and Clearing Summary(2)

OPERATIONFLAG HIGH FIELDFLAG LOW FIELDINT PIN(1)CONVERSION READY FIELD
The result register is above the high-limit register for fault count times; see the result register and the high-limit register for further details.1XActive1
The result register is below the low-limit register for fault count times; see the result register and the low-limit register for further details.X1Active1
The conversion is complete with fault count criterion not metXXActive1
Configuration register read(3)00Inactive0
Configuration register write, M[1:0] = 00b (shutdown)XXXX
Configuration register write, M[1:0] > 00b (not shutdown)XXX0
SMBus alert response protocolXXInactiveX

Note that when transitioning from end-of-conversion mode to the standard comparison modes (that is, programming LE[3:2] from 11b to 00b) when the configuration register latch field (L) is 1, a subsequent write to the configuration register latch field (L) to 0 is necessary in order to properly clear the INT pin. The latch field can then be set back to 1 if desired.

End-of-Conversion and Transparent Hysteresis-Style Comparison Mode

The combination of end-of-conversion mode and transparent hysteresis-style comparison mode can also be programmed simultaneously. The behavior of this combination is shown in Table 5.

Table 5. End-Of-Conversion Mode When in Transparent Hysteresis-Style Comparison Mode:
Flag Setting and Clearing Summary(2)

OPERATIONFLAG HIGH FIELDFLAG LOW FIELDINT PIN(1)CONVERSION READY FIELD
The result register is above the high-limit register for fault count times; see the result register and the high-limit register for further details.10Active1
The result register is below the low-limit register for fault count times; see the result register and the low-limit register for further details.01Active1
The conversion is complete with fault count criterion not metXXActive1
Configuration register read(3)XXInactive0
Configuration register write, M[1:0] = 00b (shutdown)XXXX
Configuration register write, M[1:0] > 00b (not shutdown)XXInactive0
SMBus alert response protocolXXXX

Programming

The OPT3002 supports the transmission protocol for standard mode (up to 100 kHz), fast mode (up to 400 kHz), and high-speed mode (up to 2.6 MHz). Fast and standard modes are described as the default protocol, referred to as F/S. High-speed mode is described in the High-Speed I2C Mode section.

Writing and Reading

Accessing a specific register on the OPT3002 is accomplished by writing the appropriate register address during the I2C transaction sequence. See Table 6 for a complete list of registers and the corresponding register addresses. The value for the register address (as shown in Figure 15) is the first byte transferred after the slave address byte with the R/W bit low.

OPT3002 aij_I2CPointerWr.gif

NOINDENT:

The value of the slave address byte is determined by the ADDR pin setting; see Table 1.
Figure 15. Setting the I2C Register Address Timing Diagram

Writing to a register begins with the first byte transmitted by the master. This byte is the slave address with the R/W bit low. The OPT3002 then acknowledges receipt of a valid address. The next byte transmitted by the master is the address of the register that data are to be written to. The next two bytes are written to the register addressed by the register address. The OPT3002 acknowledges receipt of each data byte. The master can terminate the data transfer by generating a start or stop condition.

When reading from the OPT3002, the last value stored in the register address by a write operation determines which register is read during a read operation. To change the register address for a read operation, a new partial I2C write transaction must be initiated. This partial write is accomplished by issuing a slave address byte with the R/W bit low, followed by the register address byte and a stop command. The master then generates a start condition and sends the slave address byte with the R/W bit high to initiate the read command. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the register address. This byte is followed by an acknowledge from the master; then the slave transmits the least significant byte. The master acknowledges receipt of the data byte. The master can terminate the data transfer by generating a not-acknowledge after receiving any data byte, or by generating a start or stop condition. If repeated reads from the same register are desired, continually sending the register address bytes is not necessary; the OPT3002 retains the register address until that number is changed by the next write operation.

Figure 16 and Figure 17 show the write and read operation timing diagrams, respectively. Note that register bytes are sent most significant byte first, followed by the least significant byte.

OPT3002 aij_I2CWrite.gif

NOINDENT:

The value of the slave address byte is determined by the setting of the ADDR pin; see Table 1.
Figure 16. I2C Write Example Timing Diagram
OPT3002 aij_I2CRead.gif

NOINDENT:

The value of the slave address byte is determined by the ADDR pin setting; see Table 1.

NOINDENT:

An ACK by the master can also be sent.
Figure 17. I2C Read Example Timing Diagram

High-Speed I2C Mode

When the bus is idle, both the SDA and SCL lines are pulled high by the pullup resistors or the active pullup devices. The master generates a start condition followed by a valid serial byte containing the high-speed (HS) master code 0000 1XXXb. This transmission is made in either standard mode or fast mode (up to 400 kHz). The OPT3002 does not acknowledge the HS master code but does recognize the code and switches its internal filters to support a 2.6-MHz operation.

The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission speeds up to 2.6 MHz are allowed. Instead of using a stop condition, use repeated start conditions to secure the bus in HS mode. A stop condition ends the HS mode and switches all internal filters of the OPT3002 to support the F/S mode.

General-Call Reset Command

The I2C general-call reset allows the host controller in one command to reset all devices on the bus that respond to the general-call reset command. The general call is initiated by writing to the I2C address 0 (0000 0000b). The reset command is initiated when the subsequent second address byte is 06h (0000 0110b). With this transaction, the device issues an acknowledge bit and sets all of its registers to the power-on-reset default condition.

SMBus Alert Response

The SMBus alert response provides a quick identification for which device issued the interrupt. Without this alert response capability, the processor does not know which device pulled the interrupt line when there are multiple slave devices connected.

The OPT3002 is designed to respond to the SMBus alert response address, when in the latched window-style comparison mode (configuration register, latch field = 1). The OPT3002 does not respond to the SMBus alert response when in transparent mode (configuration register, latch field = 0).

The response behavior of the OPT3002 to the SMBus alert response is shown in Figure 18. When the interrupt line to the processor is pulled to active, the master can broadcast the alert response slave address (0001 1001b). Following this alert response, any slave devices that generated an alert identify themselves by acknowledging the alert response and sending their respective I2C address on the bus. The alert response can activate several different slave devices simultaneously. If more than one slave attempts to respond, bus arbitration rules apply. The device with the lowest address wins the arbitration. If the OPT3002 loses the arbitration, then the device does not acknowledge the I2C transaction and its INT pin remains in an active state, prompting the I2C master processor to issue a subsequent SMBus alert response. When the OPT3002 wins the arbitration, the device acknowledges the transaction and sets its INT pin to inactive. The master can issue that same command again, as many times as necessary to clear the INT pin. See the Interrupt Reporting Mechanism Modes section for additional details of how the flags and INT pin are controlled. The master can obtain information about the source of the OPT3002 interrupt from the address broadcast in the above process. The flag high field (configuration register, bit 6) is sent as the final LSB of the address to provide the master additional information about the cause of the OPT3002 interrupt. If the master requires additional information, then the result register or the configuration register can be queried. The flag high and flag low fields are not cleared upon an SMBus alert response.

OPT3002 ai_SMBus_Alert_sbos681.gif

NOINDENT:

FH is the flag high field (FH) in the configuration register (see Table 10).

NOINDENT:

A1 and A0 are determined by the ADDR pin; see Table 1.
Figure 18. SMBus Alert Response Timing Diagram

Register Maps

Internal Registers

The device is operated over the I2C bus with registers that contain configuration, status, and result information. All registers are 16 bits long.

There are four main registers: result, configuration, low-limit, and high-limit. There is also a manufacturer ID register. Table 6 lists these registers. Do not write or read registers that are not shown on this register map.

Table 6. Register Map

REGISTERADDRESS (Hex)1514131211109876543210
Result00hE3E2E1E0R11R10R9R8R7R6R5R4R3R2R1R0
Configuration01hRN3RN2RN1RN0CTM1M0OVFCRFFHFLLPOLMEFC1FC0
Low-limit02hLE3LE2LE1LE0TL11TL10TL9TL8TL7TL6TL5TL4TL3TL2TL1TL0
High-limit03hHE3HE2HE1HE0TH11TH10TH9TH8TH7TH6TH5TH4TH3TH2TH1TH0
Manufacturer ID7EhID15ID14ID13ID12ID11ID10ID9ID8ID7ID6ID5ID4ID3ID2ID1ID0

Register Descriptions

Result Register (address = 00h)

This register contains the result of the most recent light-to-digital conversion. This 16-bit register has two fields: a 4-bit exponent and a 12-bit mantissa.

Figure 19. Result Register (Read-Only)
15141312111098
E3E2E1E0R11R10R9R8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
R7R6R5R4R3R2R1R0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read only; -n = value after reset

Table 7. Result Register Field Descriptions

BitFieldTypeResetDescription
15-12E[3:0]R0hExponent.
These bits are the exponent bits. Table 8 provides further details.
11-0R[11:0]R000hFractional result.
These bits are the result in straight binary coding (zero to full-scale).

Table 8. Result Register: Full-Scale Range (FSR) and LSB Size as a Function of Exponent Level

E3E2E1E0FSR AT 505-nm WAVELENGTH
(nW/cm2)
LSB WEIGHT AT 505-nm WAVELENGTH
(nW/cm2)
00004,9141.2
00019,8282.4
001019,6564.8
001139,3129.6
010078,62419.2
0101157,24838.4
0110314,49676.8
0111628,992153.6
10001,257,984307.2
10012,515,968614.4
10105,031,9361,228.8
101110,063,8722,457.6

The formula to translate this register into optical power is given in Equation 1:

Equation 1. Optical_Power = R[11:0] × LSB_Size

where

  • LSB_Size = 2E[3:0] × 1.2 [nW/cm2]

LSB_Size can also be taken from Table 8. The complete optical power equation is shown in Equation 2:

Equation 2. Optical_Power = (2E[3:0]) × R[11:0] × 1.2 [nW/cm2]

A series of result register output examples with the corresponding LSB weight and resulting optical power are given in Table 9. Note that many combinations of exponents (E[3:0]) and fractional results (R[11:0]) can map onto the same optical power result, as shown in the examples of Table 9.

Table 9. Examples of Decoding the Result Register into Optical Power

RESULT REGISTER
(Bits 15-0, Binary)
EXPONENT
(E[3:0], Hex)
FRACTIONAL RESULT
(R[11:0], Hex)
LSB WEIGHT AT 505-nm WAVELENGTH
(nW/cm2, Decimal)
RESULTING OPTICAL POWER AT 505-nm WAVELENGTH
(nW/cm2, Decimal)
0000 0000 0000 0001b00h001h1.21.2
0000 1111 1111 1111b00hFFFh1.24,914
0011 0100 0101 0110b03h456h9.6 338,227.2
0111 1000 1001 1010b 07h89Ah153.6629,145.6
1000 1000 0000 0000b08h800h307.2629,145.6
1001 0100 0000 0000b09h400h614.4629,145.6
1010 0010 0000 0000b0Ah200h1228.8629,145.6
1011 0001 0000 0000b0Bh100h2457.6629,145.6
1011 0000 0000 0001b0Bh001h2457.62457.6
1011 1111 1111 1111b 0BhFFFh2457.610,063,872

To compensate for the spectral response of the device, for input wavelengths other than 505 nm, see the Compensation for the Spectral Response section.

Note that the exponent field can be disabled (set to zero) by enabling the exponent mask (configuration register, ME field = 1) and manually programming the full-scale range (configuration register, RN[3:0] < 1100b (0Ch)), allowing for simpler operation in a manually-programmed, full-scale mode. Calculating optical power from the result register contents only requires multiplying the result register by the LSB weight (in nW/cm2) associated with the specific programmed full-scale range (see Table 8). See the low-limit register for details.

See the configuration register conversion time field (CT, bit 11) description for more information on optical power measurement resolution as a function of conversion time.

Configuration Register (address = 01h) [reset = C810h]

This register controls the major operational modes of the device. This register has 11 fields, as documented in this section. If a measurement conversion is in progress when the configuration register is written, then the active measurement conversion immediately aborts. If the new configuration register directs a new conversion, then that conversion is subsequently started.

Figure 20. Configuration Register
15141312111098
RN3RN2RN1RN0CTM1M0OVF
R/W-1hR/W-1hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR-0h
76543210
CRFFHFLLPOLMEFC1FC0
R-0hR-0hR-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. Configuration Register Field Descriptions

BitFieldTypeResetDescription
15-12RN[3:0]R/W0ChRange number field (read or write).
The range number field selects the full-scale optical power range of the device. The format of this field is the same as the result register exponent field (E[3:0]); see Table 8.
When RN[3:0] is set to 1100b (0Ch), the device operates in automatic full-scale setting mode, as described in the Automatic Full-Scale Setting Mode section. In this mode, the automatically chosen range is reported in the result exponent (register 00h, E[3:0]).
The device powers up as 1100 in automatic full-scale setting mode.
Codes 1101b, 1110b, and 1111b (0Dh, 0Eh, and 0Fh) are reserved for future use.
11CTR/W1hConversion time field (read or write).
The conversion time field determines the length of the light-to-digital conversion process.
The choices are 100 ms and 800 ms. A longer integration time allows for a lower noise measurement.
The conversion time also relates to the effective resolution of the data conversion process.
The 800-ms conversion time allows for the fully specified optical power resolution. The 100-ms conversion time with full-scale ranges above 0101b for E[3:0] in the result and configuration registers also allows for the fully specified optical power resolution. The 100-ms conversion time with full-scale ranges below and including 0101b for E[3:0] can reduce the effective result resolution by up to three bits, as a function of the selected full-scale range. Range 0101b reduces by one bit. Ranges 0100b, 0011b, 0010b, and 0001b reduce by two bits. Range 0000b reduces by three bits. The result register format and associated LSB weight does not change as a function of the conversion time.
0 = 100 ms
1 = 800 ms
10-9M[1:0]R/W0hMode of conversion operation field (read or write).
The mode of conversion operation field controls whether the device is operating in continuous conversion, single-shot, or low-power shutdown mode. The default is 00b (shutdown mode), such that upon power-up, the device only consumes an operational level of power after appropriately programming the device.
When single-shot mode is selected by writing 01b to this field, the field continues to read 01b when the device is actively converting. When the single-shot conversion is complete, the mode of conversion operation field is automatically set to 00b and the device is shut down.
When the device enters shutdown mode, either by completing a single-shot conversion or by a manual write to the configuration register, there is no change to the state of the reporting flags (conversion ready, flag high, flag low) or the INT pin. These signals are retained for subsequent read operations when the device is in shutdown mode.
00 = Shutdown (default)
01 = Single-shot
10, 11 = Continuous conversions
8OVFR0hOverflow flag field (read-only).
The overflow flag field indicates when an overflow condition occurs in the data conversion process, typically because the light illuminating the device exceeds the programmed full-scale range of the device. Under this condition OVF is set to 1, otherwise OVF remains at 0. The field is reevaluated on every measurement.
If the full-scale range is manually set (RN[3:0] field < 1100b), the overflow flag field can be set when the result register reports a value less than full-scale. This result occurs if the input light has a temporary high spike level that temporarily overloads the integrating ADC converter circuitry but returns to a level within range before the conversion is complete. Thus, the overflow flag reports a possible error in the conversion process. This behavior is common to integrating-style converters.
If the full-scale range is automatically set (RN[3:0] field = 1100b), the only condition that sets the overflow flag field is if the input light is beyond the full-scale level of the entire device. When there is an overflow condition and the full-scale range is not at maximum, the OPT3002 aborts the current conversion, sets the full-scale range to a higher level, and starts a new conversion. The flag is set at the end of the process. This process repeats until there is either no overflow condition or until the full-scale range is set to its maximum range.
7CRFR0hConversion ready field (read-only).
The conversion ready field indicates when a conversion completes. The field is set to 1 at the end of a conversion and is cleared (set to 0) when the configuration register is subsequently read or written with any value except for one containing the shutdown mode (mode of operation field, M[1:0] = 00b). Writing a shutdown mode does not affect the state of this field; see the Interrupt Reporting Mechanism Modes section for more details.
6FHR0hFlag high field (read-only).
The flag high field (FH) identifies that the result of a conversion is larger than a specified level of interest. FH is set to 1 when the result is larger than the level in the high-limit register (register address 03h) for a consecutive number of measurements defined by the fault count field (FC[1:0]). See the Interrupt Reporting Mechanism Modes section for more details on clearing and other behaviors of this field.
5FLR0hFlag low field (read-only).
The flag low field (FL) identifies that the result of a conversion is smaller than a specified level of interest. FL is set to 1 when the result is smaller than the level in the low-limit register (register address 02h) for a consecutive number of measurements defined by the fault count field (FC[1:0]). See the Interrupt Reporting Mechanism Modes section for more details on clearing and other behaviors of this field.
4LR/W1hLatch field (read or write).
The latch field controls the functionality of the interrupt reporting mechanisms: the INT pin, the flag high field (FH), and flag low field (FL). This bit selects the reporting style between a latched window-style comparison and a transparent hysteresis-style comparison.
0 = The device functions in transparent hysteresis-style comparison operation, where the three interrupt reporting mechanisms directly reflect the comparison of the result register with the high- and low-limit registers with no user-controlled clearing event. See the Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms section for further details.
1 = The device functions in latched window-style comparison operation, latching the interrupt reporting mechanisms until a user-controlled clearing event.
3POLR/W0hPolarity field (read or write).
The polarity field controls the polarity or active state of the INT pin.
0 = The INT pin reports active low, pulling the pin low upon an interrupt event.
1 = Operation of the INT pin is inverted, where the INT pin reports active high, becoming high impedance and allowing the INT pin to be pulled high upon an interrupt event.
2MER/W0hMask exponent field (read or write).
The mask exponent field forces the result register exponent field (register 00h, bits E[3:0]) to 0000b when the full-scale range is manually set, which can simplify the processing of the result register when the full-scale range is manually programmed. This behavior occurs when the mask exponent field is set to 1 and the range number field (RN[3:0]) is set to less than 1100b. Note that the masking is only performed on the result register. When using the interrupt reporting mechanisms, the result comparison with the low-limit and high-limit registers is unaffected by the ME field.
1-0FC[1:0]R/W0hFault count field (read or write).
The fault count field instructs the device as to how many consecutive fault events are required to trigger the interrupt reporting mechanisms: the INT pin, the flag high field (FH), and flag low field (FL). The fault events are described in the latch field (L), flag high field (FH), and flag low field (FL) descriptions.
00 = One fault count (default)
01 = Two fault counts
10 = Four fault counts
11 = Eight fault counts

Low-Limit Register (address = 02h) [reset = C0000h]

This register sets the lower comparison limit for the interrupt reporting mechanisms: the INT pin, the flag high field (FH), and flag low field (FL), as described in the Interrupt Reporting Mechanism Modes section.

Figure 21. Low-Limit Register
15141312111098
LE3LE2LE1LE0TL11TL10TL9TL8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TL7TL6TL5TL4TL3TL2TL1TL0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 11. Low-Limit Register Field Descriptions

BitFieldTypeResetDescription
15-12LE[3:0]R/W0hExponent.
These bits are the exponent bits. Table 12 provides further details.
11-0TL[11:0]R/W000hResult.
These bits are the result in straight binary coding (zero to full-scale).

The format of this register is nearly identical to the format of the result register. The low-limit register exponent (LE[3:0]) is similar to the result register exponent (E[3:0]). The low-limit register result (TL[11:0]) is similar to the result register result (R[11:0]).

The equation to translate this register into the optical power threshold is given in Equation 3, which is similar to the equation for the result register, Equation 2.

Equation 3. Optical_Power = 1.2 × (2LE[3:0]) × TL[11:0]

Table 12 gives the full-scale range and LSB size of the low-limit register. The detailed discussion and examples given for the result register apply to the low-limit register as well.

Table 12. Low Limit Register: Full-Scale Range (FSR) and LSB Size as a Function of Exponent Level

LE3LE2LE1LE0FSR AT 505-nm WAVELENGTH
(nW/cm2)
LSB WEIGHT AT 505-nm WAVELENGTH
(nW/cm2)
00004,9141.2
00019,8282.4
001019,6564.8
001139,3129.6
010078,62419.2
0101157,24838.4
0110314,49676.8
0111628,992153.6
10001,257,984307.2
10012,515,968614.4
10105,031,9361,228.8
101110,063,8722,457.6

NOTE

The result and limit registers are all converted into optical power values internally for comparison. These registers can have different exponent fields. However, when using a manually-set, full-scale range (configuration register, RN < 0Ch, with mask enable (ME) active), programming the manually-set, full-scale range into the LE[3:0] and HE[3:0] fields can simplify the choice of programming the register. This simplification results in only having to consider the fractional result and not the exponent part of the result.

High-Limit Register (address = 03h) [reset = BFFFh]

The high-limit register sets the upper comparison limit for the interrupt reporting mechanisms: the INT pin, the flag high field (FH), and flag low field (FL), as described in the Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms section. The format of this register is almost identical to the format of the low-limit register and the result register. To explain the similarity in more detail, the high-limit register exponent (HE[3:0]) is similar to the low-limit register exponent (LE[3:0]) and the result register exponent (E[3:0]). The high-limit register result (TH[11:0]) is similar to the low-limit result (TH[11:0]) and the result register result (R[11:0]). Note that the comparison of the high-limit register with the result register is unaffected by the ME bit.

When using a manually-set, full-scale range with the mask enable (ME) active, programming the manually-set, full-scale range into the HE[3:0] bits can simplify the choice of values required to program into this register. The formula to translate this register into optical power is similar to Equation 3. The full-scale values are similar to Table 8.

Figure 22. High-Limit Register
15141312111098
HE3HE2HE1HE0TH11TH10TH9TH8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TH7TH6TH5TH4TH3TH2TH1TH0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 13. High-Limit Register Field Descriptions

BitFieldTypeResetDescription
15-12HE[3:0]R/WBhExponent.
These bits are the exponent bits.
11-0TH[11:0]R/WFFFhResult.
These bits are the result in straight binary coding (zero to full-scale).

Manufacturer ID Register (address = 7Eh) [reset = 5449h]

This register is intended to help identify the device.

Figure 23. Manufacturer ID Register
15141312111098
ID15ID14ID13ID12ID11ID10ID9ID8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
ID7ID6ID5ID4ID3ID2ID1ID0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read only; -n = value after reset

Table 14. Manufacturer ID Register Field Descriptions

BitFieldTypeResetDescription
15-0ID[15:0]R5449hManufacturer ID.
The manufacturer ID reads 5449h. In ASCII code, this register reads TI.