SBOS745A May 2016  – June 2016 OPT3002

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6Timing Requirements
    7. 6.7Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1Automatic Full-Scale Range Setting
      2. 7.3.2Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
      3. 7.3.3I2C Bus Overview
        1. 7.3.3.1Serial Bus Address
        2. 7.3.3.2Serial Interface
    4. 7.4Device Functional Modes
      1. 7.4.1Automatic Full-Scale Setting Mode
      2. 7.4.2Interrupt Reporting Mechanism Modes
        1. 7.4.2.1Latched Window-Style Comparison Mode
        2. 7.4.2.2Transparent Hysteresis-Style Comparison Mode
        3. 7.4.2.3End-of-Conversion Mode
        4. 7.4.2.4End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
    5. 7.5Programming
      1. 7.5.1Writing and Reading
        1. 7.5.1.1High-Speed I2C Mode
        2. 7.5.1.2General-Call Reset Command
        3. 7.5.1.3SMBus Alert Response
    6. 7.6Register Maps
      1. 7.6.1Internal Registers
        1. 7.6.1.1Register Descriptions
          1. 7.6.1.1.1Result Register (address = 00h)
          2. 7.6.1.1.2Configuration Register (address = 01h) [reset = C810h]
          3. 7.6.1.1.3Low-Limit Register (address = 02h) [reset = C0000h]
          4. 7.6.1.1.4High-Limit Register (address = 03h) [reset = BFFFh]
          5. 7.6.1.1.5Manufacturer ID Register (address = 7Eh) [reset = 5449h]
  8. Application and Implementation
    1. 8.1Application Information
      1. 8.1.1Electrical Interface
      2. 8.1.2Optical Interface
      3. 8.1.3Compensation for the Spectral Response
    2. 8.2Do's and Don'ts
  9. Power-Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Documentation Support
      1. 11.1.1Related Documentation
    2. 11.2Receiving Notification of Documentation Updates
    3. 11.3Community Resources
    4. 11.4Trademarks
    5. 11.5Electrostatic Discharge Caution
    6. 11.6Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1Soldering and Handling Recommendations
    2. 12.2DNP (S-PDSO-N6) Mechanical Drawings

Specifications

Absolute Maximum Ratings(1)

MINMAXUNIT
VoltageVDD to GND–0.56V
SDA, SCL, INT, and ADDR to GND–0.56
Current into any pin10mA
Temperature Junction, TJ150°C
Storage, Tstg–65150(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Long exposure to temperatures higher than 105°C can cause package discoloration, spectral distortion, and measurement inaccuracy.

ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±2000V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

MINNOMMAXUNIT
Operating power-supply voltage 1.6 3.6V
Operating temperature–40 85°C

Thermal Information

THERMAL METRIC(1)OPT3002UNIT
DNP (USON)
6 PINS
RθJAJunction-to-ambient thermal resistance71.2°C/W
RθJC(top)Junction-to-case (top) thermal resistance45.7°C/W
RθJBJunction-to-board thermal resistance42.2°C/W
ψJTJunction-to-top characterization parameter2.4°C/W
ψJBJunction-to-board characterization parameter42.8°C/W
RθJC(bot)Junction-to-case (bottom) thermal resistance17.0°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics

at TA = 25°C, VDD = 3.3 V, 800-ms conversion time (CT = 1)(3), automatic full-scale range (RN[3:0] = 1100b(3)), 505-nm LED stimulus, and normal-angle incidence of light (unless otherwise specified)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
OPTICAL
Peak irradiance spectral responsivity505nm
Resolution (LSB) at 505 nm Lowest full-scale range (FSR), RN[3:0] = 0000b(3)1.2nW/cm2(1)
Full-scale illuminance at 505 nm10.064mW/cm2(1)
Measurement output result505-nm LED stimulus, FSR setting = 628,992 (nW/cm2), 153.6 (nW/cm2) per ADC code (RN[3:0] = 0111)(3)384,000nW/cm2(1)
2500ADC codes
2 klux white LED stimulus, FSR setting = 628,992 (nW/cm2), 153.6 (nW/cm2) per ADC code (RN[3:0] = 0111)(3)(4)225025002750ADC codes
Relative accuracy between gain ranges(2)0.2%
Infrared response (850 nm) relative to response at 505 nm(4)20%
LinearityInput illuminance > 5000 nW/cm2 2%
Input illuminance < 5000 nW/cm2 5%
Dark condition, ADC outputLowest FSR, RN[3:0] = 0000b, 4914 (nW/cm2), 1.2 (nW/cm2) per ADC code03ADC codes
Half-power angle50% of full-power reading60Degrees
PSRRPower-supply rejection ratioVDD at 3.6 V and 1.6 V0.1%/V(5)
POWER SUPPLY
VI²C I2C pullup resistor operating rangeI2C pullup resistor, VDD ≤ VI²C1.65.5V
IQQuiescent currentDarkActive, VDD = 3.6 V1.82.5µA
Shutdown (M[1:0] = 00)(3), VDD = 3.6 V0.30.47
Full-scale rangeActive, VDD = 3.6 V3.7
Shutdown,
(M[1:0] = 00)(3)
0.4
PORPower-on-reset thresholdTA = 25°C0.8V
DIGITAL
I/O pin capacitance3pF
Total integration time(6)(CT = 1)(3), 800-ms mode, fixed FSR720800880ms
(CT = 0)(3), 100-ms mode, fixed FSR90100110
VILLow-level input voltage
(SDA, SCL, and ADDR)
00.3 × VDDV
VIHHigh-level input voltage
(SDA, SCL, and ADDR)
0.7 × VDD5.5V
IILLow-level input current
(SDA, SCL, and ADDR)
0.010.25(7)µA
VOLLow-level output voltage
(SDA and INT)
IOL = 3 mA0.32V
IZHOutput logic high, high-Z leakage current (SDA, INT)At VDD pin0.01 0.25(7)µA
All nW/cm2 units assume a 505-nm stimulus. To scale the LSB size, full-scale, and results at other wavelengths, see the Compensation for the Spectral Response section.
Characterized by measuring fixed near-full-scale light levels on the higher adjacent full-scale range setting.
Refers to a control field within the configuration register.
Tested with the white LED calibrated to 2 klux and an 850-nm LED.
PSRR is the percent change of the measured optical power output from its current value, divided by the change in power-supply voltage, as characterized by results from the 3.6-V and 1.6-V power supplies.
The conversion time, from start of conversion until data are ready to be read, is the integration time plus 3 ms.
The specified leakage current is dominated by the production test equipment limitations. Typical values are much smaller.

Timing Requirements(1)

MINTYPMAXUNIT
I2C FAST MODE
fSCL SCL operating frequency0.010.4MHz
tBUFBus free time between stop and start1300ns
tHDSTAHold time after repeated start600ns
tSUSTASetup time for repeated start600ns
tSUSTOSetup time for stop600ns
tHDDAT Data hold time20900ns
tSUDATData setup time100ns
tLOW SCL clock low period1300ns
tHIGHSCL clock high period600ns
tRC and tFCClock rise and fall time300ns
tRD and tFDData rise and fall time300ns
tTIMEOBus timeout period. If the SCL line is held low for this duration of time, then the bus state machine is reset.28ms
I2C HIGH-SPEED MODE
fSCL SCL operating frequency0.012.6MHz
tBUFBus free time between stop and start160ns
tHDSTAHold time after repeated start160ns
tSUSTASetup time for repeated start160ns
tSUSTOSetup time for stop160ns
tHDDAT Data hold time20140 ns
tSUDATData setup time20 ns
tLOW SCL clock low period240 ns
tHIGHSCL clock high period60ns
tRC and tFCClock rise and fall time40ns
tRD and tFDData rise and fall time80ns
tTIMEOBus timeout period. If the SCL line is held low for this duration of time, then the bus state machine is reset.28ms
All timing parameters are referenced to low and high voltage thresholds of 30% and 70%, respectively, of the final settled value.
OPT3002 aij_I2C_Timing_R2.gif Figure 1. I2C Detailed Timing Diagram

Typical Characteristics

at TA = 25°C, VDD = 3.3 V, 800-ms conversion time (CT = 1), automatic full-scale range (RN[3:0] = 1100b), white LED, and normal-angle incidence of light (unless otherwise specified)
OPT3002 D001_SBOS745.gif
Figure 2. Spectral Response vs Wavelength
OPT3002 D007_SBOS745.gif
Input illuminance = 298,800 nW/cm2,
normalized to response of 314,496 nW/cm2 full-scale
Figure 4. Full-Scale-Range Matching (Highest 6 Ranges)
OPT3002 D008_SBOS745.gif
Figure 6. Normalized Response vs Temperature
OPT3002 D009_SBOS681.gif
Figure 8. Normalized Response vs Power-Supply Voltage
OPT3002 D011_SBOS745.gif
M[1:0] = 10b, illuminance derived from white LED
Figure 10. Supply Current in Active State vs
Input Illuminance
OPT3002 D013_SBOS681.gif
M[1:0] = 10b
Figure 12. Supply Current in Active State vs Temperature
OPT3002 D015_SBOS681.gif
SCL = SDA, continuously toggled at I2C frequency
Note: A typical application runs at a lower duty cycle and thus consumes a lower current.
Figure 14. Supply Current in Shutdown State vs Continuous I2C Frequency
OPT3002 D006_SBOS745.gif
Input illuminance = 3960 nW/cm2,
normalized to response of 4914 nW/cm2 full-scale
Figure 3. Full-Scale-Range Matching (Lowest 7 Ranges)
OPT3002 D016_SBOS745.gif
Average of 30 devices
Figure 5. Dark Response vs Temperature
OPT3002 D017_SBOS681.gif
Figure 7. Conversion Time vs Power Supply
OPT3002 D010_SBOS745.gif
Figure 9. Normalized Response vs Incidence Angle
OPT3002 D012_SBOS745.gif
M[1:0] = 00b, illuminance derived from white LED
Figure 11. Supply Current in Shutdown State vs
Input Illuminance
OPT3002 D014_SBOS681.gif
M[1:0] = 00b, input illuminance = 0 nW/cm2
Figure 13. Supply Current in Shutdown State vs Temperature