SLES248A May 2009  – March 2015 PCM1795

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6Timing Requirements
    7. 6.7Typical Characteristics
      1. 6.7.1Digital Filter
      2. 6.7.2Digital Filter: De-Emphasis Filter
      3. 6.7.3Analog Dynamic Performance: Supply Voltage Characteristics
      4. 6.7.4Analog Dynamic Performance: Temperature Characteristics
      5. 6.7.5Analog FIR Filter performance in DSD Mode
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1Audio Data Interface
        1. 7.3.1.1Audio Serial Interface
        2. 7.3.1.2PCM Audio Data Formats and Timing
        3. 7.3.1.3External Digital Filter Interface and Timing
        4. 7.3.1.4Direct Stream Digital (DSD) Format Interface and Timing
        5. 7.3.1.5TDMCA Interface
        6. 7.3.1.6Analog Output
    4. 7.4Device Functional Modes
    5. 7.5Programming
      1. 7.5.1System Clock and Reset Functions
        1. 7.5.1.1System Clock Input
        2. 7.5.1.2Power-On and External Reset Functions
      2. 7.5.2Function Descriptions
        1. 7.5.2.1Zero Detect
      3. 7.5.3Serial Control Interface
        1. 7.5.3.1SPI Interface
        2. 7.5.3.2Register Read/Write Operation
      4. 7.5.4I2C Interface
        1. 7.5.4.1Slave Address
        2. 7.5.4.2Packet Protocol
        3. 7.5.4.3Write Register
        4. 7.5.4.4Read Register
        5. 7.5.4.5Noise Suppression
    6. 7.6Register Maps
      1. 7.6.1Mode Control Registers
        1. 7.6.1.1User-Programmable Mode Controls
        2. 7.6.1.2Register Map
        3. 7.6.1.3Register Definitions
          1. 7.6.1.3.1 R/W: Read/Write Mode Select
          2. 7.6.1.3.2 ATx[7:0]: Digital Attenuation Level Setting
          3. 7.6.1.3.3 R/W: Read/Write Mode Select
          4. 7.6.1.3.4 ATLD: Attenuation Load Control
          5. 7.6.1.3.5 FMT[2:0]: Audio Interface Data Format
          6. 7.6.1.3.6 DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
          7. 7.6.1.3.7 DME: Digital De-Emphasis Control
          8. 7.6.1.3.8 MUTE: Soft Mute Control
          9. 7.6.1.3.9 R/W: Read/Write Mode Select
          10. 7.6.1.3.10REV: Output Phase Reversal
          11. 7.6.1.3.11ATS[1:0]: Attenuation Rate Select
          12. 7.6.1.3.12OPE: DAC Operation Control
          13. 7.6.1.3.13DFMS: Stereo DF Bypass Mode Select
          14. 7.6.1.3.14FLT: Digital Filter Roll-Off Control
          15. 7.6.1.3.15INZD: Infinite Zero Detect Mute Control
          16. 7.6.1.3.16R/W: Read/Write Mode Select
          17. 7.6.1.3.17SRST: System Reset Control
          18. 7.6.1.3.18DSD: DSD Interface Mode Control
          19. 7.6.1.3.19DFTH: Digital Filter Bypass (or Through Mode) Control
          20. 7.6.1.3.20MONO: Monaural Mode Selection
          21. 7.6.1.3.21CHSL: Channel Selection for Monaural Mode
          22. 7.6.1.3.22OS[1:0]: ΔΣ Oversampling Rate Selection
          23. 7.6.1.3.23R/W: Read/Write Mode Select
          24. 7.6.1.3.24DZ[1:0]: DSD Zero Output Enable
          25. 7.6.1.3.25PCMZ: PCM Zero Output Enable
          26. 7.6.1.3.26R: Read Mode Select
          27. 7.6.1.3.27ZFGx: Zero-Detection Flag
          28. 7.6.1.3.28Read Mode Select
          29. 7.6.1.3.29ID[4:0]: Device ID
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Applications
      1. 8.2.1Typical Connection Diagram in PCM Mode
        1. 8.2.1.1Design Requirements
        2. 8.2.1.2Detailed Design Procedure
          1. 8.2.1.2.1I/V Section
          2. 8.2.1.2.2Differential Section
        3. 8.2.1.3Application Curves
      2. 8.2.2Application for External Digital Filter Interface
        1. 8.2.2.1Design Requirements
        2. 8.2.2.2Detailed Design Procedure
          1. 8.2.2.2.1Application for Interfacing With an External Digital Filter
          2. 8.2.2.2.2Pin Assignment When Using the External Digital Filter Interface
          3. 8.2.2.2.3Audio Format
          4. 8.2.2.2.4System Clock (SCK) and Interface Timing
          5. 8.2.2.2.5Functions Available in the External Digital Filter Mode
            1. 8.2.2.2.5.1FMT[2:0]: Audio Data Format Selection
            2. 8.2.2.2.5.2OS[1:0]: ΔΣ Modulator Oversampling Rate Selection
        3. 8.2.2.3Application Curves
      3. 8.2.3Application for DSD Format (DSD Mode) Interface
        1. 8.2.3.1Design Requirements
        2. 8.2.3.2Detailed Design Procedure
          1. 8.2.3.2.1Features
          2. 8.2.3.2.2Pin Assignment When Using DSD Format Interface
          3. 8.2.3.2.3Requirements for System Clock
          4. 8.2.3.2.4DSD Mode Configuration and Function Controls
            1. 8.2.3.2.4.1Configuration for the DSD Interface Mode
            2. 8.2.3.2.4.2DMF[1:0]: Analog-FIR Performance Selection
            3. 8.2.3.2.4.3OS[1:0]: Analog-FIR Operation-Speed Selection
        3. 8.2.3.3Application Curves
      4. 8.2.4TDMCA Interface Format
        1. 8.2.4.1Design Requirements
        2. 8.2.4.2Detailed Design Procedure
          1. 8.2.4.2.1 TDMCA Mode Determination
          2. 8.2.4.2.2 TDMCA Terminals
          3. 8.2.4.2.3 Device ID Determination
          4. 8.2.4.2.4 TDMCA Frame
          5. 8.2.4.2.5 Command Field
            1. 8.2.4.2.5.1Bit 31: Device ID Enable Flag
            2. 8.2.4.2.5.2Bit 30: Extended Command Enable Flag
            3. 8.2.4.2.5.3Bit 29: Daisy-Chain Selection Flag
            4. 8.2.4.2.5.4Bits[28:24]: Device ID
            5. 8.2.4.2.5.5Bit 23: Command Read/Write flag
            6. 8.2.4.2.5.6Bits[22:16]: Register ID
            7. 8.2.4.2.5.7Bits[15:8]: Command data
            8. 8.2.4.2.5.8Bits[7:0]: Not used
          6. 8.2.4.2.6 Extended Command Field
          7. 8.2.4.2.7 Audio Fields
          8. 8.2.4.2.8 TDMCA Register Requirements
          9. 8.2.4.2.9 Register Write/Read Operation
          10. 8.2.4.2.10TDMCA Mode Operation
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Device Support
      1. 11.1.1Third-Party Products Disclaimer
    2. 11.2Trademarks
    3. 11.3Electrostatic Discharge Caution
    4. 11.4Glossary
  12. 12Mechanical, Packaging, and Orderable Information

1 Features

  • 32-Bit Resolution
  • Analog Performance:
    • Dynamic Range: 123 dB
    • THD+N: 0.0005%
  • Differential Current Output: 3.9 mAPP
  • 8× Oversampling Digital Filter:
    • Stop-Band Attenuation: –98 dB
    • Passband Ripple: ±0.0002 dB
  • Sampling Frequency: 10 kHz to 200 kHz
  • System Clock: 128, 192, 256, 384, 512,
    or 768 fS With Autodetect
  • Accepts 16-, 24-, and 32-Bit Audio Data
  • PCM Data Formats: Standard, I2S, and Left-Justified
  • DSD Format Interface Available
  • Interface Available for Optional External Digital Filter or DSP
  • TDMCA or Serial Port (SPI™/I2C)
  • User-Programmable Mode Controls:
    • Digital Attenuation:
      0 dB to –120 dB, 0.5-dB/Step
    • Digital De-Emphasis
    • Digital Filter Roll-Off: Sharp or Slow
    • Soft Mute
    • Zero Flag for Each Output
  • Compatible With PCM1792A and PCM1796
    (Pins and Mode Controls)
  • Dual Supply Operation:
    • 5-V Analog, 3.3-V Digital
  • 5-V Tolerant Digital Inputs
  • Small SSOP-28 Package

2 Applications

  • A/V Receivers
  • SACD Players
  • DVD Players
  • HDTV Receivers
  • Car Audio Systems
  • Digital Multitrack Recorders
  • Other Applications Requiring 32-Bit Audio

3 Description

The PCM1795 device is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters (DACs) and support circuitry in a small SSOP-28 package. The data converters use TI’s advanced segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1795 provides balanced current outputs, letting the user optimize analog performance externally. The PCM1795 accepts pulse code modulation (PCM) and direct stream digital (DSD) audio data formats, thus providing an easy interface to audio digital signal processors (DSPs) and decoder chips. The PCM1795 device also interfaces with external digital filter devices such as the DF1704, DF1706, and the PMD200 from Pacific Microsonics™. Sampling rates up to 200 kHz are supported. A full set of user-programmable functions is accessible through an SPI or I2C serial control port that supports register write and readback functions. The PCM1795 device also supports the time-division-multiplexed (TDM) command and audio (TDMCA) data format.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
PCM1795SSOP (28)10.20 mm × 5.30 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Block Diagram

PCM1795 fbd_les248.gif

4 Revision History

Changes from * Revision (May 2009) to A Revision

  • Added Pin Configuration and Functions section, ESD Rating table, Recommended Operating Conditions table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go