SLES248A
May 2009 – March 2015
PCM1795
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics
6.7.1
Digital Filter
6.7.2
Digital Filter: De-Emphasis Filter
6.7.3
Analog Dynamic Performance: Supply Voltage Characteristics
6.7.4
Analog Dynamic Performance: Temperature Characteristics
6.7.5
Analog FIR Filter performance in DSD Mode
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Audio Data Interface
7.3.1.1
Audio Serial Interface
7.3.1.2
PCM Audio Data Formats and Timing
7.3.1.3
External Digital Filter Interface and Timing
7.3.1.4
Direct Stream Digital (DSD) Format Interface and Timing
7.3.1.5
TDMCA Interface
7.3.1.6
Analog Output
7.4
Device Functional Modes
7.5
Programming
7.5.1
System Clock and Reset Functions
7.5.1.1
System Clock Input
7.5.1.2
Power-On and External Reset Functions
7.5.2
Function Descriptions
7.5.2.1
Zero Detect
7.5.3
Serial Control Interface
7.5.3.1
SPI Interface
7.5.3.2
Register Read/Write Operation
7.5.4
I2C Interface
7.5.4.1
Slave Address
7.5.4.2
Packet Protocol
7.5.4.3
Write Register
7.5.4.4
Read Register
7.5.4.5
Noise Suppression
7.6
Register Maps
7.6.1
Mode Control Registers
7.6.1.1
User-Programmable Mode Controls
7.6.1.2
Register Map
7.6.1.3
Register Definitions
7.6.1.3.1
R/W: Read/Write Mode Select
7.6.1.3.2
ATx[7:0]: Digital Attenuation Level Setting
7.6.1.3.3
R/W: Read/Write Mode Select
7.6.1.3.4
ATLD: Attenuation Load Control
7.6.1.3.5
FMT[2:0]: Audio Interface Data Format
7.6.1.3.6
DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
7.6.1.3.7
DME: Digital De-Emphasis Control
7.6.1.3.8
MUTE: Soft Mute Control
7.6.1.3.9
R/W: Read/Write Mode Select
7.6.1.3.10
REV: Output Phase Reversal
7.6.1.3.11
ATS[1:0]: Attenuation Rate Select
7.6.1.3.12
OPE: DAC Operation Control
7.6.1.3.13
DFMS: Stereo DF Bypass Mode Select
7.6.1.3.14
FLT: Digital Filter Roll-Off Control
7.6.1.3.15
INZD: Infinite Zero Detect Mute Control
7.6.1.3.16
R/W: Read/Write Mode Select
7.6.1.3.17
SRST: System Reset Control
7.6.1.3.18
DSD: DSD Interface Mode Control
7.6.1.3.19
DFTH: Digital Filter Bypass (or Through Mode) Control
7.6.1.3.20
MONO: Monaural Mode Selection
7.6.1.3.21
CHSL: Channel Selection for Monaural Mode
7.6.1.3.22
OS[1:0]: ΔΣ Oversampling Rate Selection
7.6.1.3.23
R/W: Read/Write Mode Select
7.6.1.3.24
DZ[1:0]: DSD Zero Output Enable
7.6.1.3.25
PCMZ: PCM Zero Output Enable
7.6.1.3.26
R: Read Mode Select
7.6.1.3.27
ZFGx: Zero-Detection Flag
7.6.1.3.28
Read Mode Select
7.6.1.3.29
ID[4:0]: Device ID
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Typical Connection Diagram in PCM Mode
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
I/V Section
8.2.1.2.2
Differential Section
8.2.1.3
Application Curves
8.2.2
Application for External Digital Filter Interface
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.2.1
Application for Interfacing With an External Digital Filter
8.2.2.2.2
Pin Assignment When Using the External Digital Filter Interface
8.2.2.2.3
Audio Format
8.2.2.2.4
System Clock (SCK) and Interface Timing
8.2.2.2.5
Functions Available in the External Digital Filter Mode
8.2.2.2.5.1
FMT[2:0]: Audio Data Format Selection
8.2.2.2.5.2
OS[1:0]: ΔΣ Modulator Oversampling Rate Selection
8.2.2.3
Application Curves
8.2.3
Application for DSD Format (DSD Mode) Interface
8.2.3.1
Design Requirements
8.2.3.2
Detailed Design Procedure
8.2.3.2.1
Features
8.2.3.2.2
Pin Assignment When Using DSD Format Interface
8.2.3.2.3
Requirements for System Clock
8.2.3.2.4
DSD Mode Configuration and Function Controls
8.2.3.2.4.1
Configuration for the DSD Interface Mode
8.2.3.2.4.2
DMF[1:0]: Analog-FIR Performance Selection
8.2.3.2.4.3
OS[1:0]: Analog-FIR Operation-Speed Selection
8.2.3.3
Application Curves
8.2.4
TDMCA Interface Format
8.2.4.1
Design Requirements
8.2.4.2
Detailed Design Procedure
8.2.4.2.1
TDMCA Mode Determination
8.2.4.2.2
TDMCA Terminals
8.2.4.2.3
Device ID Determination
8.2.4.2.4
TDMCA Frame
8.2.4.2.5
Command Field
8.2.4.2.5.1
Bit 31: Device ID Enable Flag
8.2.4.2.5.2
Bit 30: Extended Command Enable Flag
8.2.4.2.5.3
Bit 29: Daisy-Chain Selection Flag
8.2.4.2.5.4
Bits[28:24]: Device ID
8.2.4.2.5.5
Bit 23: Command Read/Write flag
8.2.4.2.5.6
Bits[22:16]: Register ID
8.2.4.2.5.7
Bits[15:8]: Command data
8.2.4.2.5.8
Bits[7:0]: Not used
8.2.4.2.6
Extended Command Field
8.2.4.2.7
Audio Fields
8.2.4.2.8
TDMCA Register Requirements
8.2.4.2.9
Register Write/Read Operation
8.2.4.2.10
TDMCA Mode Operation
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.2
Trademarks
11.3
Electrostatic Discharge Caution
11.4
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DB|28
MPDS510A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sles248a_oa
sles248a_pm