SLASE64A December   2014  – June 2017 PCM1860-Q1 , PCM1861-Q1 , PCM1862-Q1 , PCM1863-Q1 , PCM1864-Q1 , PCM1865-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: PGA and ADC AC Performance
    6. 7.6  Electrical Characteristics: DC
    7. 7.7  Electrical Characteristics: Digital Filter
    8. 7.8  Timing Requirements: External Clock
    9. 7.9  Timing Requirements: I2C Control Interface
    10. 7.10 Timing Requirements: SPI Control Interface
    11. 7.11 Timing Requirements: Audio Data Interface for Slave Mode
    12. 7.12 Timing Requirements: Audio Data Interface for Master Mode
    13. 7.13 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Features Description
      1. 9.3.1  Analog Front End
      2. 9.3.2  Microphone Support
        1. 9.3.2.1 Mic Bias
      3. 9.3.3  Input Multiplexer (PCM1860-Q1 and PCM1861-Q1)
      4. 9.3.4  Mixers and Multiplexers (PCM1862-Q1, PCM1863-Q1, PCM1864-Q1, and PCM1865-Q1)
      5. 9.3.5  Programmable Gain Amplifier
      6. 9.3.6  Automatic Clipping Suppression
        1. 9.3.6.1 Attenuation Level
        2. 9.3.6.2 Channel Linking
      7. 9.3.7  Zero Crossing Detect
      8. 9.3.8  Digital Inputs
        1. 9.3.8.1 Stereo PCM Sources
        2. 9.3.8.2 Digital PDM Microphones
      9. 9.3.9  Clocks
        1. 9.3.9.1 Description
        2. 9.3.9.2 External Clock-Source Limits
        3. 9.3.9.3 Device Clock Distribution and Generation
        4. 9.3.9.4 Clocking Modes
          1. 9.3.9.4.1 Clock Configuration and Selection for Hardware-Controlled Devices
          2. 9.3.9.4.2 Clock Sources for Software-Controlled Devices
          3. 9.3.9.4.3 Clocking Configuration and Selection for Software-Controlled Devices
            1. 9.3.9.4.3.1 Target Clock Rates for ADC, DSP1 and DSP2
            2. 9.3.9.4.3.2 Configuration of Master Mode
          4. 9.3.9.4.4 BCK Input Slave PLL Mode
          5. 9.3.9.4.5 Software-Controlled Devices ADC Non-Audio MCK PLL Mode
        5. 9.3.9.5 Software-Controlled Devices Manual PLL Calculation
        6. 9.3.9.6 Clock Halt and Error
        7. 9.3.9.7 Clock Halt and Error Detect
        8. 9.3.9.8 Changes in Clock Sources and Sample Rates
      10. 9.3.10 Analog-to-Digital Converters (ADCs)
        1. 9.3.10.1 Main Audio ADCs
        2. 9.3.10.2 Secondary ADC: Energysense and Analog Control
          1. 9.3.10.2.1 Secondary ADC Analog Input Range
          2. 9.3.10.2.2 Frequency Response of the Secondary ADC
        3. 9.3.10.3 Secondary ADC Controlsense DC Level Change Detection
      11. 9.3.11 Energysense
        1. 9.3.11.1 Energysense Signal Loss Flag
        2. 9.3.11.2 Energysense Signal Detect Circuitry
          1. 9.3.11.2.1 Energysense Threshold Levels for Both Signal Loss and Signal Detect
        3. 9.3.11.3 Programming Various Coefficients for Energysense
      12. 9.3.12 Audio Processing
        1. 9.3.12.1 DSP1 Processing Features
          1. 9.3.12.1.1 Digital Decimation Filters
          2. 9.3.12.1.2 Digital PGA
        2. 9.3.12.2 DSP2 Processing Features
          1. 9.3.12.2.1 Digital Mixing Function
      13. 9.3.13 Fade-In and Fade-Out Functions
      14. 9.3.14 Mappable GPIO Pins
      15. 9.3.15 Interrupt Controller
        1. 9.3.15.1 DIN Toggle Detection
        2. 9.3.15.2 Clearing Interrupts
          1. 9.3.15.2.1 Reset Energysense Loss (in Active Mode)
          2. 9.3.15.2.2 Reset Energysense Detect (In Sleep Mode)
          3. 9.3.15.2.3 Reset Controlsense (Active and Sleep Modes)
          4. 9.3.15.2.4 Reset DIN Toggle (In Sleep Mode)
          5. 9.3.15.2.5 Reset PGA Clipping (Active)
      16. 9.3.16 Audio Format Selection and Timing Details
        1. 9.3.16.1 Audio Format Selection
        2. 9.3.16.2 Serial Audio Interface Timing Details
        3. 9.3.16.3 Digital Audio Output 2 Configuration
        4. 9.3.16.4 Time Division Multiplex (TDM Support)
        5. 9.3.16.5 Decimation Filter Select
        6. 9.3.16.6 Serial Audio Data Interface Configuration
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Mode Descriptions
        1. 9.4.1.1 PCM1860-Q1 and PCM1861-Q1 Hardware Device Power Down Functions
          1. 9.4.1.1.1 Enter Standby Mode (From Active Mode)
          2. 9.4.1.1.2 Exit From Standby Mode Back to Active
          3. 9.4.1.1.3 Enter or Exit Sleep or Energysense Mode to Active
        2. 9.4.1.2 PCM186x-Q1 Software Device Power Down Functions
          1. 9.4.1.2.1 Enter or Exit Stand-by Mode
          2. 9.4.1.2.2 Enter Sleep Mode
          3. 9.4.1.2.3 Exit Sleep Mode
        3. 9.4.1.3 Bypassing the Internal LDO to Reduce Power Consumption
    5. 9.5 Programming
      1. 9.5.1 Control
        1. 9.5.1.1 Hardware Control Configuration
        2. 9.5.1.2 Software-Controlled Device Configuration
        3. 9.5.1.3 SPI Interface
          1. 9.5.1.3.1 Register Read and Write Operation
        4. 9.5.1.4 I2C Interface
          1. 9.5.1.4.1 Slave Address
          2. 9.5.1.4.2 Packet Protocol
      2. 9.5.2 Current Status Registers
      3. 9.5.3 Real World Software Configuration using Energysense and Controlsense
        1. 9.5.3.1 Active Mode Flow Diagram
        2. 9.5.3.2 Basic Device Configuration
        3. 9.5.3.3 Clear Energysense Interrupt
        4. 9.5.3.4 Update System Settings
        5. 9.5.3.5 Sleep Mode Flow Diagram
        6. 9.5.3.6 Update Controlsense values in Sleep Mode
          1. 9.5.3.6.1 Update System Settings
      4. 9.5.4 Programming and Register Reference
        1. 9.5.4.1 Coefficient Data Formats
      5. 9.5.5 Programming DSP Coefficients on Software-Controlled Devices
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Device Control Method
        1. 10.1.1.1 Hardware Control
        2. 10.1.1.2 Software Control
          1. 10.1.1.2.1 SPI Control
          2. 10.1.1.2.2 I2C Control
      2. 10.1.2 Power-Supply Options
        1. 10.1.2.1 3.3-V AVDD, DVDD, and IOVDD
        2. 10.1.2.2 3.3-V AVDD, DVDD, and 1.8-V IOVDD
      3. 10.1.3 Master Clock Source
      4. 10.1.4 Dual PCM186x-Q1 TDM Functionality
      5. 10.1.5 Analog Input Configuration
        1. 10.1.5.1 Analog Front-End Circuit For Single-Ended, Line-In Applications
        2. 10.1.5.2 Analog Front-End Circuit for Differential, Line-In Applications
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo Recording Application for PCM186x-Q1 Hardware-Controlled Devices in Master Mode
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Stereo Recording Application for PCM186x-Q1 Software-Controlled Devices in Slave PLL Mode with 1.8-V IOVDD
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Distribution and Requirements
    2. 11.2 1.8-V Support
    3. 11.3 Brownout Conditions
    4. 11.4 Power-Up Sequence
    5. 11.5 Lowest Power-Down Modes
      1. 11.5.1 Lowest Power In Standby Mode (AVDD = DVDD = IOVDD = 3.3 V)
      2. 11.5.2 Lowest Power in Sleep or Energysense Mode (AVDD = DVDD = IOVDD = 3.3 V)
      3. 11.5.3 Lower Power in Sleep or Energysense Mode (AVDD = DVDD 3.3 V and IOVDD = 1.8 V)
    6. 11.6 Power-On Reset Sequencing Timing Diagram
    7. 11.7 Power Connection Examples
      1. 11.7.1 3.3-V AVDD, DVDD, and IOVDD Example
      2. 11.7.2 3.3-V AVDD, DVDD With 1.8-V IOVDD Example for Lower-Power Applications
    8. 11.8 Fade In
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Grounding and System Partitioning
    2. 12.2 Layout Example
  13. 13Register Map
    1. 13.1 Register Map Description
    2. 13.2 Register Map Summary
    3. 13.3 Page 0 Registers
      1. 13.3.1  Page 0: Register 1 (address = 0x01) [reset = 0x00]
      2. 13.3.2  Page 0: Register 2 (address = 0x02) [reset = 0x00]
      3. 13.3.3  Page 0: Register 3 (address = 0x03) [reset = 0x00]
      4. 13.3.4  Page 0: Register 4 (address = 0x04) [reset = 0x00]
      5. 13.3.5  Page 0: Register 5 (address = 0x05) [reset = 0x86]
      6. 13.3.6  Page 0: Register 6 (address = 0x06) [reset = 0x41]
      7. 13.3.7  Page 0: Register 7 (address = 0x07) [reset = 0x41]
      8. 13.3.8  Page 0: Register 8 (address = 0x08) [reset = 0x42]
      9. 13.3.9  Page 0: Register 9 (address = 0x09) [reset = 0x42]
      10. 13.3.10 Page 0: Register 10 (address = 0x0A) [reset = 0x00]
      11. 13.3.11 Page 0: Register 11 (address = 0x0B) [reset = 0x44]
      12. 13.3.12 Page 0: Register 12 (address = 0x0C) [reset = 0x00]
      13. 13.3.13 Page 0: Register 13 (address = 0x0D) [reset = 0x00]
      14. 13.3.14 Page 0: Register 14 (address = 0x0E) [reset = 0x00]
      15. 13.3.15 Page 0: Register 15 (address = 0x0F) [reset = 0x00]
      16. 13.3.16 Page 0: Register 16 (address = 0x10) [reset = 0x01]
      17. 13.3.17 Page 0: Register 17 (address = 0x11) [reset = 0x20]
      18. 13.3.18 Page 0: Register 18 (address = 0x12) [reset = 0x00]
      19. 13.3.19 Page 0: Register 19 (address = 0x13) [reset = 0x00]
      20. 13.3.20 Page 0: Register 20 (address = 0x14) [reset = 0x00]
      21. 13.3.21 Page 0: Register 21 (address = 0x15) [reset = 0x00]
      22. 13.3.22 Page 0: Register 22 (address = 0x16) [reset = 0x00]
      23. 13.3.23 Page 0: Register 23 (address = 0x17) [reset = 0x00]
      24. 13.3.24 Page 0: Register 24 (address = 0x18) [reset = 0x00]
      25. 13.3.25 Page 0: Register 25 (address = 0x19) [reset = 0x00]
      26. 13.3.26 Page 0: Register 26 (address = 0x1A) [reset = 0x00]
      27. 13.3.27 Page 0: Register 27 (address = 0x1B) [reset = 0x00]
      28. 13.3.28 Page 0: Register 32 (address = 0x20) [reset = 0x01]
      29. 13.3.29 Page 0: Register 33 (address = 0x21) [reset = 0x00]
      30. 13.3.30 Page 0: Register 34 (address = 0x22) [reset = 0x01]
      31. 13.3.31 Page 0: Register 35 (address = 0x23) [reset = 0x03]
      32. 13.3.32 Page 0: Register 37 (address = 0x25) [reset = 0x07]
      33. 13.3.33 Page 0: Register 38 (address = 0x26) [reset = 0x03]
      34. 13.3.34 Page 0: Register 39 (address = 0x27) [reset = 0x3F]
      35. 13.3.35 Page 0: Register 40 (address = 0x28) [reset = 0x01]
      36. 13.3.36 Page 0: Register 41 (address = 0x29) [reset = 0x00]
      37. 13.3.37 Page 0: Register 42 (address = 0x2A) [reset = 0x00]
      38. 13.3.38 Page 0: Register 43 (address = 0x2B) [reset = 0x01]
      39. 13.3.39 Page 0: Register 44 (address = 0x2C) [reset = 0x00]
      40. 13.3.40 Page 0: Register 45 (address = 0x2D) [reset = 0x00]
      41. 13.3.41 Page 0: Register 48 (address = 0x30) [reset = 0x00]
      42. 13.3.42 Page 0: Register 49 (address = 0x31) [reset = 0x00]
      43. 13.3.43 Page 0: Register 50 (address = 0x32) [reset = 0x00]
      44. 13.3.44 Page 0: Register 51 (address = 0x33) [reset = 0x00]
      45. 13.3.45 Page 0: Register 52 (address = 0x34) [reset = 0x00]
      46. 13.3.46 Page 0: Register 54 (address = 0x36) [reset = 0x01]
      47. 13.3.47 Page 0: Register 64 (address = 0x40) [reset =0x80]
      48. 13.3.48 Page 0: Register 65 (address = 0x41) [reset = 0x7F]
      49. 13.3.49 Page 0: Register 66 (address = 0x42) [reset = 0x00]
      50. 13.3.50 Page 0: Register 67 (address = 0x43) [reset = 0x80]
      51. 13.3.51 Page 0: Register 68 (address = 0x44) [reset = 0x7F]
      52. 13.3.52 Page 0: Register 69 (address = 0x45) [reset = 0x00]
      53. 13.3.53 Page 0: Register 70 (address = 0x46) [reset = 0x80]
      54. 13.3.54 Page 0: Register 71 (address = 0x47) [reset = 0x7F]
      55. 13.3.55 Page 0: Register 72 (address = 0x48) [reset = 0x00]
      56. 13.3.56 Page 0: Register 73 (address = 0x49) [reset = 0x80]
      57. 13.3.57 Page 0: Register 74 (address = 0x4A) [reset = 0x7F]
      58. 13.3.58 Page 0: Register 75 (address = 0x4B) [reset = 0x00]
      59. 13.3.59 Page 0: Register 76 (address = 0x4C) [reset = 0x80]
      60. 13.3.60 Page 0: Register 77 (address = 0x4D) [reset = 0x7F]
      61. 13.3.61 Page 0: Register 78 (address = 0x4E) [reset = 0x00]
      62. 13.3.62 Page 0: Register 79 (address = 0x4F) [reset = 0x80]
      63. 13.3.63 Page 0: Register 80 (address = 0x50) [reset = 0x7F]
      64. 13.3.64 Page 0: Register 81 (address = 0x51) [reset = 0x00]
      65. 13.3.65 Page 0: Register 82 (address = 0x52) [reset = 0x80]
      66. 13.3.66 Page 0: Register 83 (address = 0x53) [reset = 0x7F]
      67. 13.3.67 Page 0: Register 84 (address = 0x54) [reset = 0x00]
      68. 13.3.68 Page 0: Register 85 (address = 0x55) [reset = 0x80]
      69. 13.3.69 Page 0: Register 86 (address = 0x56) [reset = 0x7F]
      70. 13.3.70 Page 0: Register 87 (address = 0x57) [reset = 0x00]
      71. 13.3.71 Page 0: Register 88 (address = 0x58) [reset = 0x00]
      72. 13.3.72 Page 0: Register 89 (address = 0x59) [reset = 0x00]
      73. 13.3.73 Page 0: Register 90 (address = 0x5A) [reset = 0x00]
      74. 13.3.74 Page 0: Register 96 (address = 0x60) [reset = 0x01]
      75. 13.3.75 Page 0: Register 97 (address = 0x61) [reset = 0x00]
      76. 13.3.76 Page 0: Register 98 (address = 0x62) [reset =0x10]
      77. 13.3.77 Page 0: Register 112 (address = 0x70) [reset = 0x70]
      78. 13.3.78 Page 0: Register 113 (address = 0x71) [reset = 0x10]
      79. 13.3.79 Page 0: Register 114 (address = 0x72) [reset = 0x00]
      80. 13.3.80 Page 0: Register 115 (address = 0x73) [reset = 0x00]
      81. 13.3.81 Page 0: Register 116 (address = 0x74) [reset = 0x00]
      82. 13.3.82 Page 0: Register 117 (address = 0x75) [reset = 0x00]
      83. 13.3.83 Page 0: Register 120 (address = 0x78) [reset = 0x00]
    4. 13.4 Page 1 Registers
      1. 13.4.1  Page 1: Register 1 (address = 0x01) [reset = 0x00]
      2. 13.4.2  Page 1: Register 2 (address = 0x02) [reset = 0x00]
      3. 13.4.3  Page 1: Register 4 (address = 0x04) [reset = 0x00]
      4. 13.4.4  Page 1: Register 5 (address = 0x05) [reset = 0x00]
      5. 13.4.5  Page 1: Register 6 (address = 0x06) [reset = 0x00]
      6. 13.4.6  Page 1: Register 7 (address = 0x07) [reset = 0x00]
      7. 13.4.7  Page 1: Register 8 (address = 0x08) [reset = 0x00]
      8. 13.4.8  Page 1: Register 9 (address = 0x09) [reset = 0x00]
      9. 13.4.9  Page 1: Register 10 (address = 0x0A) [reset = 0x00]
      10. 13.4.10 Page 1: Register 11 (address = 0x0B) [reset = 0x00]
    5. 13.5 Page 3 Registers
      1. 13.5.1 Page 3: Register 18 (address = 0x12) [reset =0x40]
      2. 13.5.2 Page 3: Register 21 (address = 0x15) [reset = 0x01]
    6. 13.6 Page 253 Registers
      1. 13.6.1 Page 253: Register 20 (address = 0x14) [reset = 0x00]
  14. 14Device and Documentation Support
    1. 14.1 Development Support
    2. 14.2 Related Links
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 Community Resources
    5. 14.5 Trademarks
    6. 14.6 Electrostatic Discharge Caution
    7. 14.7 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Register Map

13.1 Register Map Description

The register map is the primary way to configure the PCM186x-Q1 software-controlled devices. The register map is separated into four pages: 0,1,3, and 253. Page 0 handles all of the device configuration. Page 1 is used to indirectly program coefficients into the two fixed function DSPs on the PCM186x-Q1. Page 3 and page 253 contain additional registers for lower-power use. All undocumented registers are considered reserved; do not write to undocumented registers.

Change pages by writing to register 0x00 with the required page.

Reset registers by writing 0xFE to register 0x00.

13.2 Register Map Summary

Table 25. Register Map Summary

DEC HEX BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Page 0
1 0x01 PGA_VAL_CH1_L
2 0x02 PGA_VAL_CH1_R
3 0x03 PGA_VAL_CH2_L
4 0x04 PGA_VAL_CH2_R
5 0x05 SMOOTH LINK DPGA_CLIP_EN MAX_ATT START_ATT AGC_EN
6 0x06 POL RSV SEL_L
7 0x07 POL RSV SEL_R
8 0x08 POL RSV SEL_L
9 0x09 POL RSV SEL_R
10 0x0A RSV SEL
11 0x0B RX_WLEN RSV TDM_LRCK_MODE TX_WLEN FMT
12 0x0C RSV TDM_OSEL
13 0x0D TX_TDM_OFFSET
14 0x0E RX_TDM_OFFSET
15 0x0F DPGA_VAL_CH1_L
16 0x10 GPIO1_POL GPIO1_FUNC GPIO0_POL GPIO0_FUNC
17 0x11 GPIO3_POL GPIO3_FUNC GPIO2_POL GPIO2_FUNC
18 0x12 RSV GPIO1_DIR RSV GPIO0_DIR2
19 0x13 RSV GPIO3_DIR2 RSV GPIO2_DIR2
20 0x14 GPIO3_OUT GPIO2_OUT GPIO1_OUT GPIO0_OUT GPIO3_IN GPIO2_IN GPIO1_IN GPIO0_IN
21 0x15 PULL_DOWN_DIS[3] PULL_DOWN_DIS[2] PULL_DOWN_DIS[1] PULL_DOWN_DIS[0] RSV
22 0x16 DPGA_VAL_CH1_R
23 0x17 DPGA_VAL_CH2_L
24 0x18 DPGA_VAL_CH2_R
25 0x19 DPGA_CH2_R DPGA_CH2_L DPGA_CH1_R DPGA_CH1_L APGA_CH2_R APGA_CH2_L APGA_CH1_R APGA_CH1_L
26 0x1A DIGMIC_IN1_SEL DIGMIC_IN0_SEL RSV DIGMIC_4CH DIGMIC_EN
27 0x1B RSV DIN_RESAMP
32 0x20 SCK_XI_SEL MST_SCK_SRC MST_MODE ADC_CLK_SRC DSP2_CLK_SRC DSP1_CLK_SRC CLKDET_EN
33 0x21 RSV DIV_NUM
34 0x22 RSV DIV_NUM
35 0x23 RSV DIV_NUM
37 0x25 RSV DIV_NUM
38 0x26 RSV DIV_NUM
39 0x27 DIV_NUM
40 0x28 RSV LOCK RSV PLL_REF_SEL PLL_EN
41 0x29 RSV P
42 0x2A RSV R
43 0x2B RSV J
44 0x2C D_LSB
45 0x2D RSV D_MSB
48 0x30 CH4R CH4L CH3R CH3L CH2R CH2L CH1R CH1L
49 0x31 CH4R CH4L CH3R CH3L CH2R CH2L CH1R CH1L
50 0x32 CH4R CH4L CH3R CH3L CH2R CH2L CH1R CH1L
51 0x33 RSV TIME
52 0x34 RSV TIME
54 0x36 RSV INT_INTVL
64 0x40 REF
65 0x41 DIFF
66 0x42 LEVEL
67 0x43 REF
68 0x44 DIFF
69 0x45 LEVEL
70 0x46 REF
71 0x47 DIFF
72 0x48 LEVEL
73 0x49 REF
74 0x4A DIFF
75 0x4B LEVEL
76 0x4C REF
77 0x4D DIFF
78 0x4E LEVEL
79 0x4F REF
80 0x50 DIFF
81 0x51 LEVEL
82 0x52 REF
83 0x53 DIFF
84 0x54 LEVEL
85 0x55 REF
86 0x56 DIFF
87 0x57 LEVEL
88 0x58 DC_NOLATCH AUXADC_RDY DC_RDY AUXADC_LATCH AUXADC_DATA_TYPE DC_CH
89 0x59 AUXADC_DATA_LSB
90 0x5A AUXADC_DATA_MSB
96 0x60 RSV POSTPGA_CP RSV DC_CHANG DIN_TOGGLE ENGSTR
97 0x61 RSV POSTPGA_CP RSV DC_CHANG DIN_TOGGLE ENGSTR
98 0x62 RSV POL1 POL0 RSV WIDTH
112 0x70 RSV PWRDN SLEEP STBY
113 0x71 2CH RSV FLT HPF_EN MUTE_CH2_R MUTE_CH2_L MUTE_CH1_R MUTE_CH1_L
114 0x72 RSV STATE
115 0x73 RSV INFO
116 0x74 RSV BCK_RATIO2 RSV SCK_RATIO2
117 0x75 RSV LRCKHLT BCKHLT SCKHTL RSV LRCKERR BCKERR SCKERR
120 0x78 RSV DVDD AVDD LDO
Page 1
1 0x01 RSV DONE RSV BUSY R_REQ W_REQ
2 0x02 RSV MEM_ADDR
4 0x04 MEM_WDATA_0
5 0x05 MEM_WDATA_1
6 0x06 MEM_WDATA_2
7 0x07 MEM_WDATA3 RSV
8 0x08 MEM_RDATA_0
9 0x09 MEM_RDATA_1
10 0x0A MEM_RDATA_2
11 0x0B MEM_RDATA_3 RSV
Page 3
18 0x12 RSV PD
21 0x15 RSV PDZ
Page 253
20 0x14 PGA_ICI REF_ICI RSV

13.3 Page 0 Registers

13.3.1 Page 0: Register 1 (address = 0x01) [reset = 0x00]

Figure 76. Page 0: Register 1
7 6 5 4 3 2 1 0
PGA_VAL_CH1_L
R/W-0000 0000b

Table 26. Page 0: Register 1 Field Descriptions

Bit Field Type Reset Description
7-0 PGA_VAL_CH1_L R/W 0000 0000b PGA Value Channel 1 Left
Global channel gain for ADC1L. (analog + digital). Analog gain only, if manual gain mapping is enabled. (0x19)
Specify two's complement value with 7.1 format.
1110 1000: –12.0 dB (Min)
…
1111 1110: –1.0 dB
1111 1111: 0.5 dB
0000 0000: 0.0 dB (default)
0000 0001: 0.5 dB
…
0000 0010: 1.0 dB
…
0001 1000: 12.0 dB
…
0010 1000: 20.0 dB
…
0100 0000: 32.0 dB
…
0101 0000: 40.0 dB (Max)

13.3.2 Page 0: Register 2 (address = 0x02) [reset = 0x00]

Figure 77. Page 0: Register 2
7 6 5 4 3 2 1 0
PGA_VAL_CH1_R
R/W-0000 0000b

Table 27. Page 0: Register 2 Field Descriptions

Bit Field Type Reset Description
7-0 PGA_VAL_CH1_R R/W 0000 0000b PGA Value Channel 1 Right
Programmable gain value, channel 1 right (see Page 0, 0x01 for complete description)

13.3.3 Page 0: Register 3 (address = 0x03) [reset = 0x00]

Figure 78. Page 0: Register 3
7 6 5 4 3 2 1 0
PGA_VAL_CH2_L
R/W-0000 0000b

Table 28. Page 0: Register 3 Field Descriptions

Bit Field Type Reset Description
7-0 PGA_VAL_CH2_L R/W 0000 0000b PGA Value Channel 2 Left
Programmable gain value, channel 2 left (see Page 0, 0x01 for complete description)

13.3.4 Page 0: Register 4 (address = 0x04) [reset = 0x00]

Figure 79. Page 0: Register 4
7 6 5 4 3 2 1 0
PGA_VAL_CH2_R
R/W-0000 0000b

Table 29. Page 0: Register 4 Field Descriptions

Bit Field Type Reset Description
7-0 PGA_VAL_CH2_R R/W 0000 0000b PGA Value Channel 2 Right
Programmable gain value, channel 2 right (see Page 0, 0x01 for complete description)

13.3.5 Page 0: Register 5 (address = 0x05) [reset = 0x86]

Figure 80. Page 0: Register 5
7 6 5 4 3 2 1 0
SMOOTH LINK DPGA_CLIP_EN MAX_ATT START_ATT AGC_EN
R/W-1b R/W-0b R/W-0b R/W-00b R/W-11b R/W-0b

Table 30. Page 0: Register 5 Field Descriptions

Bit Field Type Reset Description
7 SMOOTH R/W 1b

PGA Control


Enable PGA smooth change
0: Immediate change
1: Smooth change (default)
6 LINK R/W 0b Link PGA Control
0: Independent control (default)
1: Ch1[R] / Ch2[L] / Ch2[R] follow Ch1[L] PGA value.
5 DPGA_CLIP_EN R/W 0b Enable Clipping Detection After Digital PGA
0: Disable (default)
1: Enable
4-3 MAX_ATT R/W 00b Attenuation Limit of the Automatic Clipping Suppression
00: –3 dB (default)
01: –4 dB
10: –5 dB
11: –6 dB
2-1 START_ATT R/W 11b Start Automatic Clipping Suppression After Clipping is Detected CLIP_NUM Times
00: 80
01: 40
10: 20
11: 10 (default)
0 AGC_EN R/W 0b Enable Automatic Clipping Suppression
0: Disable (default)
1: Enable

13.3.6 Page 0: Register 6 (address = 0x06) [reset = 0x41]

Figure 81. Page 0: Register 6
7 6 5 4 3 2 1 0
POL RSV SEL_L
R/W-0b R/W-1b R/W-00 0001b

Table 31. Page 0: Register 6 Field Descriptions

Bit Field Type Reset Description
7 POL R/W 0b

Change ADC1_INPUT_SEL_L Signal Polarity


0: Normal (default)
1: Inverted
6 RSV R/W 1b Reserved. Always write 1.
5-0 SEL_L R/W 00 0001b ADC 1 Input Channel Select (ADC1L)
00 0000: No select
00 0001: VINL1[SE] (default)
00 0010: VINL2[SE]
00 0011: VINL2[SE] + VINL1[SE]
00 0100: VINL3[SE]
00 0101: VINL3[SE] + VINL1[SE]
00 0110: VINL3[SE] + VINL2[SE]
00 0111: VINL3[SE] + VINL2[SE] + VINL1[SE]
00 1000: VINL4[SE]
00 1001: VINL4[SE] + VINL1[SE]
00 1010: VINL4[SE] + VINL2[SE]
00 1011: VINL4[SE] + VINL2[SE] + VINL1[SE]
00 1100: VINL4[SE] + VINL3[SE]
00 1101: VINL4[SE] + VINL3[SE] + VINL1[SE]
00 1110: VINL4[SE] + VINL3[SE] + VINL2[SE]
00 1111: VINL4[SE] + VINL3[SE] + VINL2[SE] + VINL1[SE]
01 0000: {VIN1P, VIN1M}[DIFF]
10 0000: {VIN4P, VIN4M}[DIFF]
11 0000: {VIN1P, VIN1M}[DIFF] + {VIN4P, VIN4M}[DIFF]

13.3.7 Page 0: Register 7 (address = 0x07) [reset = 0x41]

Figure 82. Page 0: Register 7
7 6 5 4 3 2 1 0
POL RSV SEL_R
R/W-0b R/W-1b R/W-00 0001b

Table 32. Page 0: Register 7 Field Descriptions

Bit Field Type Reset Description
7 POL R/W 0b

Change ADC1_INPUT_SEL_R Signal Polarity


0: Normal (default)
1: Inverted
6 RSV R/W 1b Reserved. Do not access.
5-0 SEL_R R/W 00 0001b ADC 1 Input Channel Select (ADC1R)
00 0000: No select
00 0001: VINR1[SE] (default)
00 0010: VINR2[SE]
00 0011: VINR2[SE] + VINR1[SE]
00 0100: VINR3[SE]
00 0101: VINR3[SE] + VINR1[SE]
00 0110: VINR3[SE] + VINR2[SE]
00 0111: VINR3[SE] + VINR2[SE] + VINR1[SE]
00 1000: VINR4[SE]
00 1001: VINR4[SE] + VINR1[SE]
00 1010: VINR4[SE] + VINR2[SE]
00 1011: VINR4[SE] + VINR2[SE] + VINR1[SE]
00 1100: VINR4[SE] + VINR3[SE]
00 1101: VINR4[SE] + VINR3[SE] + VINR1[SE]
00 1110: VINR4[SE] + VINR3[SE] + VINR2[SE]
00 1111: VINR4[SE] + VINR3[SE] + VINR2[SE] + VINR1[SE]
01 0000: {VIN2P, VIN2M}[DIFF]
10 0000: {VIN3P, VIN3M}[DIFF]
11 0000: {VIN2P, VIN2M}[DIFF] + {VIN3P, VIN3M}[DIFF]

13.3.8 Page 0: Register 8 (address = 0x08) [reset = 0x42]

Figure 83. Page 0: Register 8
7 6 5 4 3 2 1 0
POL RSV SEL_L
R/W-0b R/W-1b R/W-00 0010b

Table 33. Page 0: Register 8 Field Descriptions

Bit Field Type Reset Description
7 POL R/W 0b

Change ADC2_INPUT_SEL_L Signal Polarity


0: Normal (default)
1: Inverted
6 RSV R/W 1b Reserved. Do not access.
5-0 SEL_L R/W 00 0010b ADC 2 Input Channel Select (ADC2L)
00 0000: No select
00 0001: VINL1[SE] (default)
00 0010: VINL2[SE]
00 0011: VINL2[SE] + VINL1[SE]
00 0100: VINL3[SE]
00 0101: VINL3[SE] + VINL1[SE]
00 0110: VINL3[SE] + VINL2[SE]
00 0111: VINL3[SE] + VINL2[SE] + VINL1[SE]
00 1000: VINL4[SE]
00 1001: VINL4[SE] + VINL1[SE]
00 1010: VINL4[SE] + VINL2[SE]
00 1011: VINL4[SE] + VINL2[SE] + VINL1[SE]
00 1100: VINL4[SE] + VINL3[SE]
00 1101: VINL4[SE] + VINL3[SE] + VINL1[SE]
00 1110: VINL4[SE] + VINL3[SE] + VINL2[SE]
00 1111: VINL4[SE] + VINL3[SE] + VINL2[SE] + VINL1[SE]
01 0000: {VIN1P, VIN1M}[DIFF]
10 0000: {VIN4P, VIN4M}[DIFF]
11 0000: {VIN1P, VIN1M}[DIFF] + {VIN4P, VIN4M}[DIFF]

13.3.9 Page 0: Register 9 (address = 0x09) [reset = 0x42]

Figure 84. Page 0: Register 9
7 6 5 4 3 2 1 0
POL RSV SEL_R
R/W-0b R/W-1b R/W-00 0010b

Table 34. Page 0: Register 9 Field Descriptions

Bit Field Type Reset Description
7 POL R/W 0b

Change ADC2_INPUT_SEL_R Signal Polarity


0: Normal (default)
1: Inverted
6 RSV R/W 1b Reserved. Do not access.
5-0 SEL_R R/W 00 0010b ADC 2 Input Channel Select (ADC2R)
00 0000: No select
00 0001: VINR1[SE] (default)
00 0010: VINR2[SE]
00 0011: VINR2[SE] + VINR1[SE]
00 0100: VINR3[SE]
00 0101: VINR3[SE] + VINR1[SE]
00 0110: VINR3[SE] + VINR2[SE]
00 0111: VINR3[SE] + VINR2[SE] + VINR1[SE]
00 1000: VINR4[SE]
00 1001: VINR4[SE] + VINR1[SE]
00 1010: VINR4[SE] + VINR2[SE]
00 1011: VINR4[SE] + VINR2[SE] + VINR1[SE]
00 1100: VINR4[SE] + VINR3[SE]
00 1101: VINR4[SE] + VINR3[SE] + VINR1[SE]
00 1110: VINR4[SE] + VINR3[SE] + VINR2[SE]
00 1111: VINR4[SE] + VINR3[SE] + VINR2[SE] + VINR1[SE]
01 0000: {VIN2P, VIN2M}[DIFF]
10 0000: {VIN3P, VIN3M}[DIFF]
11 0000: {VIN2P, VIN2M}[DIFF] + {VIN3P, VIN3M}[DIFF]

13.3.10 Page 0: Register 10 (address = 0x0A) [reset = 0x00]

Figure 85. Page 0: Register 10
7 6 5 4 3 2 1 0
RSV SEL3
R/W-0000b R/W-0000b

Table 35. Page 0: Register 10 Field Descriptions

Bit Field Type Reset Description
7-4 RSV R/W 0000b Reserved. Do not access.
3-0 SEL R/W 0000b Secondary ADC Input Channel
Do not select the same channel that is already in use by an audio ADC
0: No Select (default)
1: ch1(L)
2: ch1(R)
3: ch2(L)
4: ch2(R)
5: ch3(L)
6: ch3(R)
7: ch4(L)
8: ch4(R)

13.3.11 Page 0: Register 11 (address = 0x0B) [reset = 0x44]

Figure 86. Page 0: Register 11
7 6 5 4 3 2 1 0
RX_WLEN RSV TDM_LRCK_MODE TX_WLEN FMT
R/W-01b R/W-0 R/W-0b R/W-01b R/W-00b

Table 36. Page 0: Register 11 Field Descriptions

Bit Field Type Reset Description
7-6 RX_WLEN R/W 01b

Receive PCM Word Length


00: 32-bit
01: 24-bit (default)
10: 20-bit
11: 16-bit
5 RSV R/W 0b Reserved. Do not access.
4 TDM_LRCK_MODE R/W 0b LRCK Duty Cycle in TDM Mode
TDM format can support 2 channels, 4 channels, or 6 channels with one device.
When BCK to LRCK ratio is 256, FMT must be configured as TDM format.
Configure the duty cycle of LRCK when I2S is configured as TDM mode
0: duty cycle of LRCK is 50% (default)
1: duty cycle of LRCK is 1/256 (similar DSP mode)
3-2 TX_WLEN R/W 01b Stereo PCM Word Length
00: 32-bit
01: 24-bit (default)
10: 20-bit
11: 16-bit
1-0 FMT R/W 00b Serial Audio Interface Format (TDM/DSP Mode)
0: I2S (default)
1: Left justified
2: Right justified
3: TDM/DSP (256fS BCK is required)

13.3.12 Page 0: Register 12 (address = 0x0C) [reset = 0x00]

Figure 87. Page 0: Register 12
7 6 5 4 3 2 1 0
RSV TDM_OSEL
R/W-000000b R/W-00b

Table 37. Page 0: Register 12 Field Descriptions

Bit Field Type Reset Description
7-2 RSV R/W 000000b Reserved. Do not access.
1-0 TDM_OSEL R/W 00b Select TDM Transmission Data
Ch2 data only available on 4-channel device.
00: 2ch TDM (default)
DOUT1: ch1[L], ch1[R]
DOUT2: ch2[L], ch2[R]
01: 4ch TDM
DOUT1: ch1[L], ch1[R], ch2[L], ch2[R]
DOUT2: ch1[L], ch1[R], ch2[L], ch2[R]
10: 6ch TDM
DOUT1: ch1[L], ch1[R], ch2[L], ch2[R], sec_ADC_LPF, sec_ADC_HPF
DOUT2: ch1[L], ch1[R], ch2[L], ch2[R], sec_ADC_LPF, sec_ADC_HPF
11: RESERVED

13.3.13 Page 0: Register 13 (address = 0x0D) [reset = 0x00]

Figure 88. Page 0: Register 13
7 6 5 4 3 2 1 0
TX_TDM_OFFSET
R/W-0000 0000b

Table 38. Page 0: Register 13 Field Descriptions

Bit Field Type Reset Description
7-0 TX_TDM_OFFSET R/W 0000 0000b

Set Offset Position in Serial Audio Data Frame


This setting is enabled when 0x0B FMT[1:0] is set to DSP format.
0: 0 (default)
1: 1 BCK (same as I2S)
2: 2 BCK
3: 3 BCK
:
255: 255 BCK

13.3.14 Page 0: Register 14 (address = 0x0E) [reset = 0x00]

Figure 89. Page 0: Register 14
7 6 5 4 3 2 1 0
RX_TDM_OFFSET
R/W-0000 0000b

Table 39. Page 0: Register 14 Field Descriptions

Bit Field Type Reset Description
7-0 RX_TDM_OFFSET R/W 0000 0000b

Set Offset Position in a Serial Audio Data Frame


This setting is enabled when I2S_RX_FMT is set to DSP format.
Offset position in a serial audio data frame.
0: 0 (default)
1: 1 BCK (same as I2S, only if LRCK is configured as 50% duty cycle)
2: 2 BCK
3: 3 BCK
:
255: 255 BCK

13.3.15 Page 0: Register 15 (address = 0x0F) [reset = 0x00]

Figure 90. Page 0: Register 15
7 6 5 4 3 2 1 0
DPGA_VAL_CH1_L
R/W-0000 0000b

Table 40. Page 0: Register 15 Field Descriptions

Bit Field Type Reset Description
7-0 DPGA_VAL_CH1_L R/W 0000 0000b Gain Setting for Digital PGA Channel 1 Left
4-channel PCM186x-Q1 only when is used in following scenarios:
i. Analog PGA gain and digital PGA are set separately.
ii. Digital microphone Interface is used (when manual gain mapping is enabled in register 0x19).
Specify two's complement value with 7.1 format.
0x28 to 0x3F in 0.5-dB steps
Others: Reserved

13.3.16 Page 0: Register 16 (address = 0x10) [reset = 0x01]

Figure 91. Page 0: Register 16
7 6 5 4 3 2 1 0
GPIO1_POL GPIO1_FUNC GPIO0_POL GPIO0_FUNC
R/W-0b R/W-000b R/W-0b R/W-001b

Table 41. Page 0: Register 16 Field Descriptions

Bit Field Type Reset Description
7 GPIO1_POL R/W 0b GPIO1 Polarity Control
0: Normal (default)
1: Invert
6-4 GPIO1_FUNC R/W 000b Function select, GPIO1
000: GPIO1(default)
001: Digital mic input 1(In)
010: INT
011: Internal SCK (Out)
100: Digital mute (In)
101: DOUT2 (Out)
110: DIN (In)
111: Reserved
3 GPIO0_POL R/W 0b GPIO0 Polarity Control
0: Normal (default)
1: Invert
2-0 GPIO0_FUNC R/W 001b Function select, GPIO0
000: GPIO0
001: Digital mic input 0 (In, default)
010: SPI MISO (Ou)
011: Internal SCK (Out)
100: Digital mute (In)
101: DOUT2 (Out)
110: DIN (In)
111: Reserved

13.3.17 Page 0: Register 17 (address = 0x11) [reset = 0x20]

Figure 92. Page 0: Register 17
7 6 5 4 3 2 1 0
GPIO3_POL GPIO3_FUNC GPIO2_POL GPIO2_FUNC
R/W-0b R/W-010b R/W-0b R/W-000b

Table 42. Page 0: Register 17 Field Descriptions

Bit Field Type Reset Description
7 GPIO3_POL R/W 0b GPIO3 Polarity Control
0: Normal (default)
1: Invert
6-4 GPIO3_FUNC R/W 010b Function select, GPIO1
000: GPIO3
001: Reserved
010: INT (default)
011: Internal SCK (Out)
100: Digital mute (In)
101: DOUT2 (Out)
110: DIN (In)
111: Reserved
3 GPIO2_POL R/W 0b GPIO2 Polarity Control
0: Normal (default)
1: Invert
2-0 GPIO2_FUNC R/W 000b Function select, GPIO2
000: GPIO2 (default)
001: Digital mic clock output 0 (Out)
010: INT
011: Internal SCK (Out)
100: Digital mute (In)
101: DOUT2 (Out)
110: DIN (In)
111: Reserved

13.3.18 Page 0: Register 18 (address = 0x12) [reset = 0x00]

Figure 93. Page 0: Register 18
7 6 5 4 3 2 1 0
RSV GPIO1_DIR RSV GPIO0_DIR
R/W-0b R/W-000b R/W-0b R/W-000b

Table 43. Page 0: Register 18 Field Descriptions

Bit Field Type Reset Description
7 RSV R/W 0b Reserved. Do not access.
6-4 GPIO1_DIR R/W 000b Direction Control of GPIO1 When Configured as GPIO Function
000: Input (default)
001: Input with sticky bit
010: Input with toggle detection
011: Raw input (not deglictched)
100: Output
101: Open drain
110: Reserved
111: Reserved
3 RSV R/W 0b Reserved. Do not access.
2-0 GPIO0_DIR R/W 000b Direction Control of GPIO0 When Configured as GPIO Function
000: Input (default)
001: Input with sticky bit
010: Input with toggle detection
011: Raw input (not deglictched)
100: Output
101: Open drain
110: Reserved
111: Reserved

13.3.19 Page 0: Register 19 (address = 0x13) [reset = 0x00]

Figure 94. Page 0: Register 19
7 6 5 4 3 2 1 0
RSV GPIO3_DIR RSV GPIO2_DIR
R/W-0b R/W-000b R/W-0b R/W-000b

Table 44. Page 0: Register 19 Field Descriptions

Bit Field Type Reset Description
7 RSV R/W 0b Reserved. Do not access.
6-4 GPIO3_DIR R/W 000b Direction Control of GPIO3 When Configured as GPIO Function
000: Input (default)
001: Input with sticky bit
010: Input with toggle detection
011: Raw input (not deglictched)
100: Output
101: Open drain
110: Reserved
111: Reserved
3 RSV R/W 0b Reserved. Do not access.
2-0 GPIO2_DIR R/W 000b Direction Control of GPIO2 When Configured as GPIO Function
000: Input (default)
001: Input with sticky bit
010: Input with toggle detection
011: Raw input (not deglictched)
100: Output
101: Open drain
110: Reserved
111: Reserved

13.3.20 Page 0: Register 20 (address = 0x14) [reset = 0x00]

Figure 95. Page 0: Register 20
7 6 5 4 3 2 1 0
GPIO3_OUT GPIO2_OUT GPIO1_OUT GPIO0_OUT GPIO3_IN GPIO2_IN GPIO1_IN GPIO0_IN
R/W-0b R/W-0b R/W-0b R/W-0b R-0b R-0b R-0b R-0b

Table 45. Page 0: Register 20 Field Descriptions

Bit Field Type Reset Description
7 GPIO3_OUT R/W 0b GPIO3 Output Status
6 GPIO2_OUT R/W 0b GPIO2 Output Status
5 GPIO1_OUT R/W 0b GPIO1Output Status
4 GPIO0_OUT R/W 0b GPIO0 Output Status
3 GPIO3_IN R/W 0b GPIO3 Input Status or Toggle Status
The sticky flag is cleared when this register is read.
2 GPIO2_IN R/W 0b GPIO2 Input Status or Toggle Status
The sticky flag is cleared when this register is read.
1 GPIO1_IN R/W 0b GPIO1 Input Status or Toggle Status
The sticky flag is cleared when this register is read.
0 GPIO0_IN R/W 0b GPIO0 Input Status or Toggle Status
The sticky flag is cleared when this register is read.

13.3.21 Page 0: Register 21 (address = 0x15) [reset = 0x00]

Figure 96. Page 0: Register 21
7 6 5 4 3 2 1 0
PULL_DOWN_DIS[3] PULL_DOWN_DIS[2] PULL_DOWN_DIS[1] PULL_DOWN_DIS[0] RSV
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0000b

Table 46. Page 0: Register 21 Field Descriptions

Bit Field Type Reset Description
7 PULL_DOWN_DIS[3] R/W 0b Enable or Disable the Pull-Down Resistor of GPIO3
0: Enable the pull down of GPIO3, IntC (pin 19)
1: Disable the pull down
6 PULL_DOWN_DIS[2] R/W 0b Enable or Disable the Pull-Down Resistor of GPIO2
0: Enable the pull down of GPIO2, IntB (pin 20)
5 PULL_DOWN_DIS[1] R/W 0b Enable or Disable the Pull-Down Resistor of GPIO1
0: Enable the pull down of GPIO1 (pin 21)
1: Disable the pull down
4 PULL_DOWN_DIS[0] R/W 0b Enable or Disable the Pull-Down Resistor of GPIO0
0: Enable the pull down of GPIO0 (pin 22)
1: Disable the pull down
3-0 RSV R/W 0b Reserved. Do not access.

13.3.22 Page 0: Register 22 (address = 0x16) [reset = 0x00]

Figure 97. Page 0: Register 22
7 6 5 4 3 2 1 0
DPGA_VAL_CH1_R
R/W-0000 0000b

Table 47. Page 0: Register 22 Field Descriptions

Bit Field Type Reset Description
7-0 DPGA_VAL_CH1_R R/W 0000 0000b Gain Setting for Digital PGA Channel 1 Right
4-channel PCM186x-Q1 only when is used in following scenarios:
i. Analog PGA gain and digital PGA are set separately
ii. Digital microphone Interface is used (\when manual gain mapping is enabled in register 0x19)
Specify two's complement value with 7.1 format.
0010 1000: 0.0 dB
0010 1001: 0.5 dB
0010 1010: 1.0 dB
0010 1011: 1.5 dB
:
0011 1111: 7.5 dB (max)
Others: Reserved

13.3.23 Page 0: Register 23 (address = 0x17) [reset = 0x00]

Figure 98. Page 0: Register 23
7 6 5 4 3 2 1 0
DPGA_VAL_CH2_L
R/W-0000 0000b

Table 48. Page 0: Register 23 Field Descriptions

Bit Field Type Reset Description
7-0 DPGA_VAL_CH2_L R/W 0000 0000b Gain Setting for Digital PGA Channel 2 Left
4-channel PCM186x-Q1 only. See Page 0, Reg 0x16 description

13.3.24 Page 0: Register 24 (address = 0x18) [reset = 0x00]

Figure 99. Page 0: Register 24
7 6 5 4 3 2 1 0
DPGA_VAL_CH2_R
R/W-0000 0000b

Table 49. Page 0: Register 24 Field Descriptions

Bit Field Type Reset Description
7-0 DPGA_VAL_CH2_R R/W 0000 0000b Gain Setting for Digital PGA channel 2 Right
4-channel PCM186x-Q1 only. See Page 0, Reg 0x16 description

13.3.25 Page 0: Register 25 (address = 0x19) [reset = 0x00]

Figure 100. Page 0: Register 25
7 6 5 4 3 2 1 0
DPGA_CH2_R DPGA_CH2_L DPGA_CH1_R DPGA_CH1_L APGA_CH2_R APGA_CH2_L APGA_CH1_R APGA_CH1_L
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b

Table 50. Page 0: Register 25 Field Descriptions

Bit Field Type Reset Description
7 DPGA_CH2_R R/W 0b DPGA Control Mapping (4-channel PCM186x-Q1 only)
CH2_R channel (Note: Using manual gain mapping in the 2-channel device sets the digital gain to 0dB.)
0: Auto gain mapping (default)
1: Manual gain mapping
6 DPGA_CH2_L R/W 0b DPGA Control Mapping (4-channel PCM186x-Q1 only)
Gain control mode for digital PGA of CH2_L channel
0: Auto gain mapping (default)
1: Manual gain mapping
5 DPGA_CH1_R R/W 0b DPGA Control Mapping (4-channel PCM186x-Q1 only)
Gain control mode for digital PGA of CH1_R channel
0: Auto gain mapping (default)
1: Manual gain mapping
4 DPGA_CH1_L R/W 0b DPGA Control Mapping (4-channel PCM186x-Q1 only)
Gain control mode for digital PGA of CH1_L channel
0: Auto gain mapping (default)
1: Manual gain mapping
3 APGA_CH2_R R/W 0b APGA Control Mapping (4-channel PCM186x-Q1 only)
Gain control mode for analog PGA of CH2_R channel
0: Auto gain mapping (default)
1: Manual gain mapping
2 APGA_CH2_L R/W 0b APGA Control Mapping (4-channel PCM186x-Q1 only)
Gain control mode for analog PGA of CH2_L channel
0: Auto gain mapping (default)
1: Manual gain mapping
1 APGA_CH1_R R/W 0b APGA Control Mapping (4-channel PCM186x-Q1 only)
Gain control mode for analog PGA of CH1_R channel
0: Auto gain mapping (default)
1: Manual gain mapping
0 APGA_CH1_L R/W 0b APGA Control Mapping (4-channel PCM186x-Q1 only)
Gain control mode for analogPGA of CH1_L channel
0: Auto gain mapping (default)
1: Manual gain mapping

13.3.26 Page 0: Register 26 (address = 0x1A) [reset = 0x00]

Figure 101. Page 0: Register 26
7 6 5 4 3 2 1 0
DIGMIC_IN1_SEL DIGMIC_IN0_SEL RSV DIGMIC_4CH DIGMIC_EN
R/W-00b R/W-00b R/W-00b R/W-0b R/W-0b

Table 51. Page 0: Register 26 Field Descriptions

Bit Field Type Reset Description
7-6 DIGMIC_IN1_SEL R/W 00b Digital Mic Data Input Selection for MIC1 Interface (4-channel devices only)
00: GPIO0 (default)
01: GPIO1
10: Invalid
11: Invalid
5-4 DIGMIC_IN0_SEL R/W 00b Digital Mic Data Input Selection for MIC0 Interface
00: GPIO0 (default)
01: GPIO1
10: Invalid
11: Invalid
3-2 RSV R/W 00b Reserved. Do not access.
1 DIGMIC_4CH R/W 0b Second Pair of Filters Selection for Digital Microphone as Signal Processing (4-channel device only)
0: configured for analog ADC signal processing (default)
1: configured for digital MIC signal processing
0 DIGMIC_EN R/W 0b First Pair of Filters Selection for Digital Microphone as Signal Processing
0: configured as analog ADC signal processing (default)
1: configured as digital MIC signal processing

13.3.27 Page 0: Register 27 (address = 0x1B) [reset = 0x00]

Figure 102. Page 0: Register 27
7 6 5 4 3 2 1 0
RSV DIN_RESAMP
R/W-00 0000b R/W-00b

Table 52. Page 0: Register 27 Field Descriptions

Bit Field Type Reset Description
7-2 RSV R/W 00 0000b Reserved. Do not access.
1-0 DIN_RESAMP R/W 00b Resample DIN with Internal BCK to Avoid Internal Timing Issue
00: No resample (default)
01: resample DIN with rising edge of BCK
10: resample DIN with falling edge of BCK
11: Not supported

13.3.28 Page 0: Register 32 (address = 0x20) [reset = 0x01]

Figure 103. Page 0: Register 32
7 6 5 4 3 2 1 0
SCK_XI_SEL MST_SCK_SRC MST_MODE ADC_CLK_SRC DSP2_CLK_SRC DSP1_CLK_SRC CLKDET_EN
R/W-00b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-1b

Table 53. Page 0: Register 32 Field Descriptions

Bit Field Type Reset Description
7-6 SCK_XI_SEL R/W 00b SCK or XTAL Selection
00: SCK or XTAL (default)
01: SCK
10: XTAL
11: Reserved
5 MST_SCK_SRC R/W 0b Master-Mode SCK Source Selection
0: SCK or XI (default)
1: PLL (as in BCK PLL mode)
4 MST_MODE R/W 0b Master or Slave Selection
0: Slave (default)
1: Master
3 ADC_CLK_SRC R/W 0b ADC Clock Source Selection (ignored if CLKDET_EN = 1)
0: SCK (default)
1: PLL
2 DSP2_CLK_SRC R/W 0b DSP2 Clock Source Selection (ignored if CLKDET_EN = 1)
0: SCK (default)
1: PLL
1 DSP1_CLK_SRC R/W 0b DSP1 Clock Source Selection (ignored if CLKDET_EN = 1)
0: SCK (default)
1: PLL
0 CLKDET_EN R/W 1b Enable Auto Clock Detector Configuration
0: Disable
1: Enable (default)

13.3.29 Page 0: Register 33 (address = 0x21) [reset = 0x00]

Figure 104. Page 0: Register 33
7 6 5 4 3 2 1 0
RSV DIV_NUM
R/W-0b R/W-000 0000b

Table 54. Page 0: Register 33 Field Descriptions

Bit Field Type Reset Description
7 RSV R/W 0b Reserved. Do not access.
6-0 DIV_NUM R/W 000 0000b Set DSP1 Clock Divider Value
Ignored if CLKDET_EN = 1
0: 1 (default)
1: 1/2
2: 1/3
3: 1/4
:
127: 1/128

13.3.30 Page 0: Register 34 (address = 0x22) [reset = 0x01]

Figure 105. Page 0: Register 34
7 6 5 4 3 2 1 0
RSV DIV_NUM
R/W-0b R/W-000 0001b

Table 55. Page 0: Register 34 Field Descriptions

Bit Field Type Reset Description
7 RSV R/W 0b Reserved. Do not access.
6-0 DIV_NUM R/W 000 0001b Set DSP2 Clock Divider Value
Ignored if CLKDET_EN = 1
0: 1
1: 1/2 (default)
2: 1/3
3: 1/4
:
127: 1/128

13.3.31 Page 0: Register 35 (address = 0x23) [reset = 0x03]

Figure 106. Page 0: Register 35
7 6 5 4 3 2 1 0
RSV DIV_NUM
R/W-0b R/W-000 0011b

Table 56. Page 0: Register 35 Field Descriptions

Bit Field Type Reset Description
7 RSV R/W 0 Reserved. Do not access.
6-0 DIV_NUM R/W 000 0011b Set ADC Clock Divider Value
Ignored if CLKDET_EN = 1
0: 1
1: 1/2
2: 1/3
3: 1/4 (default)
:
127: 1/128

13.3.32 Page 0: Register 37 (address = 0x25) [reset = 0x07]

CLK_DIV_PLL_SCK is the alternate name for this register.

Figure 107. Page 0: Register 37
7 6 5 4 3 2 1 0
RSV DIVNUM
R/W-0b R/W-000 0111b

Table 57. Page 0: Register 37 Field Descriptions

Bit Field Type Reset Description
7 RSV R/W 0 Reserved. Do not access.
6-0 DIV_NUM R/W 000 0111b Set PLL SCK Clock Output Divider for SCK Out (when enabled)
Used in BCK slave mode or master mode where PLL-ed SCK Out is required. Requires MST_SCK_SRC (0x20) to be enabled.
Divider value:
0: 1
1: 1/2
2: 1/3
3: 1/4
:
7: 1/8 (default)
:
127: 1/128

13.3.33 Page 0: Register 38 (address = 0x26) [reset = 0x03]

CLK_DIV_SCK_BCK is the alternate name for this register.

Figure 108. Page 0: Register 38
7 6 5 4 3 2 1 0
RSV DIVNUM
R/W-0b R/W-000 0011b

Table 58. Page 0: Register 38 Field Descriptions

Bit Field Type Reset Description
7 RSV R/W 0 Reserved. Do not access.
6-0 DIV_NUM R/W 000 0011b Set Master Clock (SCK) to BCK Divider Value
Ratio of master clock (SCK) to bit clock (BCK) in master mode
Divider value:
0: 1
1: 1/2
2: 1/3
3: 1/4 (default)
:
7: 1/8
:
127: 1/128

13.3.34 Page 0: Register 39 (address = 0x27) [reset = 0x3F]

CLK_DIV_BCK_LRCK is the alternate name for this register.

Figure 109. Page 0: Register 39
7 6 5 4 3 2 1 0
DIV_NUM
R/W-0011 1111b

Table 59. Page 0: Register 39 Field Descriptions

Bit Field Type Reset Description
7-0 DIV_NUM R/W 0011 1111b Set the Master SCK Clock Value
SCK to LRCK ratio in master mode
Divider value:
0: 1
1: 1/2
2: 1/3
3: 1/4
:
63: 1/64 (default)
:
127: 1/128
:
255: 1/256

13.3.35 Page 0: Register 40 (address = 0x28) [reset = 0x01]

Figure 110. Page 0: Register 40
7 6 5 4 3 2 1 0
RSV LOCK RSV PLL_REF_SEL PLL_EN
R/W-000b R/W-0b R/W-00b R/W-0b R/W-1b

Table 60. Page 0: Register 40 Field Descriptions

Bit Field Type Reset Description
7-5 RSV R/W 000b Reserved. Do not access.
4 LOCK R/W 0b PLL Lock Status
0: Not locked (default)
1: Locked
3-2 RSV R/W 00b Reserved. Do not access.
1 PLL_REF_SEL R/W 0b PLL Reference Clock Selection
Ignored if CLKDET_EN = 1
0: SCK (default)
1: BCK
0 PLL_EN R/W 1b PLL Enable
Ignored if CLKDET_EN = 1
0: Disable
1: Enable (default)

13.3.36 Page 0: Register 41 (address = 0x29) [reset = 0x00]

Figure 111. Page 0: Register 41
7 6 5 4 3 2 1 0
RSV P
R/W-0b R/W-000 0000b

Table 61. Page 0: Register 41 Field Descriptions

Bit Field Type Reset Description
7 RSV R/W 0b Reserved. Do not access.
6-0 R/W 000 0000b PLL P Divider Value
Ignored if CLKDET_EN = 1
0: 1 (default)
1: 1/2
2: 1/3
3: 1/4
:
127: 1/128

13.3.37 Page 0: Register 42 (address = 0x2A) [reset = 0x00]

Figure 112. Page 0: Register 42
7 6 5 4 3 2 1 0
RSV R
R/W-0000b R/W-0000b

Table 62. Page 0: Register 42 Field Descriptions

Bit Field Type Reset Description
7-4 RSV R/W 0000b Reserved. Do not access.
3-0 R R/W 0000b PLL R Multiplier Value
Ignored if CLKDET_EN = 1
0: 1 (default)
1: 2
2: 3
3: 4
:
15 16

13.3.38 Page 0: Register 43 (address = 0x2B) [reset = 0x01]

Figure 113. Page 0: Register 43
7 6 5 4 3 2 1 0
RSV J
R/W-0b R/W-000 0001b

Table 63. Page 0: Register 43 Field Descriptions

Bit Field Type Reset Description
7 RSV R/W 0b Reserved. Do not access.
6-0 J R/W 000 0001b Integer Part of PLL J.D Multiplier Value
Ignored if CLKDET_EN = 1
0: (Prohibit)
1: 1 (default)
2: 2
:
63: 63

13.3.39 Page 0: Register 44 (address = 0x2C) [reset = 0x00]

Figure 114. Page 0: Register 44
7 6 5 4 3 2 1 0
D_LSB
R/W-0000 0000b

Table 64. Page 0: Register 44 Field Descriptions

Bit Field Type Reset Description
7-0 D_LSB R/W 0000 0000b Fractional Part of PLL J.D-Multiplier Value (least significant bits)
Ignored if CLKDET_EN = 1
0: 0 (default)
1: 1
2: 2
:
9999: 9999 (0x270F for both registers combined)

13.3.40 Page 0: Register 45 (address = 0x2D) [reset = 0x00]

Figure 115. Page 0: Register 45
7 6 5 4 3 2 1 0
RSV D_MSB
R/W-00b R/W-00 0000b

Table 65. Page 0: Register 45 Field Descriptions

Bit Field Type Reset Description
7-6 RSV R/W 00b Reserved. Do not access.
5-0 D_MSB R/W 00 0000b Fractional Part of PLL J.D Multiplier Value. (most significant bits, [13:8])
Ignored if CLKDET_EN = 1
0: 0 (default)
1: 1
2: 2
:
9999: 9999 (0x270F for both registers combined)

13.3.41 Page 0: Register 48 (address = 0x30) [reset = 0x00]

SIGDET_CH_MODE is the alternate name for this register.

Figure 116. Page 0: Register 48
7 6 5 4 3 2 1 0
CH4R CH4L CH3R CH3L CH2R CH2L CH1R CH1L
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b

Table 66. Page 0: Register 48 Field Descriptions

Bit Field Type Reset Description
7 CH4R R/W 0b Signal Detection Mode for Channel 4 Right
Select the signal detection mode for each channel in SLEEP mode
0: Audio signal detection (default)
1: DC level-change detection
6 CH4L R/W 0b Signal Detection Mode for Channel 4 Left
Select the signal detection mode for each channel in SLEEP mode
0: Audio signal detection (default)
1: DC level-change detection
5 CH3R R/W 0b Signal Detection Mode for Channel 3 Right
Select the signal detection mode for each channel in SLEEP mode
0: Audio signal detection (default)
1: DC level-change detection
4 CH3L R/W 0b Signal Detection Mode for Channel 3 Left
Select the signal detection mode for each channel in SLEEP mode
0: Audio signal detection (default)
1: DC level-change detection
3 CH2R R/W 0b Signal Detection Mode for Channel 2 Right
Select the signal detection mode for each channel in SLEEP mode
0: Audio signal detection (default)
1: DC level-change detection
2 CH2L R/W 0b Signal Detection Mode for Channel 2 Left
Select the signal detection mode for each channel in SLEEP mode
0: Audio signal detection (default)
1: DC level-change detection
1 CH1R R/W 0b Signal Detection Mode for Channel 1 Right
Select the signal detection mode for each channel in SLEEP mode
0: Audio signal detection (default)
1: DC level-change detection
0 CH1L R/W 0b Signal Detection Mode for Channel 1 Left
Select the signal detection mode for each channel in SLEEP mode
0: Audio signal detection (default)
1: DC level-change detection

13.3.42 Page 0: Register 49 (address = 0x31) [reset = 0x00]

SIGDET_TRIG_MASK is the alternate name for this register.

Figure 117. Page 0: Register 49
7 6 5 4 3 2 1 0
CH4R CH4L CH3R CH3L CH2R CH2L CH1R CH1L
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b

Table 67. Page 0: Register 49 Field Descriptions

Bit Field Type Reset Description
7 CH4R R/W 0b Mask Bits of Interrupt Trigger for Channel 4 Right
All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register
0: No mask (default)
1: Mask
6 CH4L R/W 0b Mask Bits of Interrupt Trigger for Channel 4 Left
All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register
0: No mask (default)
1: Mask
5 CH3R R/W 0b Mask Bits of Interrupt Trigger for Channel 3 Right
All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register
0: No mask (default)
1: Mask
4 CH3L R/W 0b Mask Bits of Interrupt Trigger for Channel 3 Left
All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register
0: No mask (default)
1: Mask
3 CH2R R/W 0b Mask Bits of Interrupt Trigger for Channel 2 Right
All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register
0: No mask (default)
1: Mask
2 CH2L R/W 0b Mask Bits of Interrupt Trigger for Channel 2 Left
All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register
0: No mask (default)
1: Mask
1 CH1R R/W 0b Mask Bits of Interrupt Trigger for Channel 1 Right
All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register
0: No mask (default)
1: Mask
0 CH1L R/W 0b Mask Bits of Interrupt Trigger for Channel 1 Left
All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register
0: No mask (default)
1: Mask

13.3.43 Page 0: Register 50 (address = 0x32) [reset = 0x00]

SIGDET_STAT is the alternate name for this register.

Figure 118. Page 0: Register 50
7 6 5 4 3 2 1 0
CH4R CH4L CH3R CH3L CH2R CH2L CH1R CH1L
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b

Table 68. Page 0: Register 50 Field Descriptions

Bit Field Type Reset Description
7 CH4R R/W 0b Status of Signal Level Detection in Both Energysense and Controlsense Modes (read only). Field column indicates respective channel.
A) In audio signal detection mode:
a) In the active or run state:
0: Signal active
1: Signal lost
b) In the sleep mode
0: Signal lost
1: Signal active
In automatic clipping suppression mode:
0: No change
1: changed DC level
6 CH4L R/W 0b
5 CH3R R/W 0b
4 CH3L R/W 0b
3 CH2R R/W 0b
2 CH2L R/W 0b
1 CH1R R/W 0b
0 CH1L R/W 0b

13.3.44 Page 0: Register 51 (address = 0x33) [reset = 0x00]

SIGDET_LOSS_TIME is the alternate name for this register.

Figure 119. Page 0: Register 51
7 6 5 4 3 2 1 0
RSV TIME
R/W-000b R/W-0 0001b

Table 69. Page 0: Register 51 Field Descriptions

Bit Field Type Reset Description
7-5 RSV R/W 000 Reserved. Do not access.
4-0 TIME R/W 0 0001b If the signal drops below the threshold on the current audio input for this set amount of time, the device generates an interrupt
0: Prohibit
1: 1 minute (default)
2: 2 minutes
3: 3 minutes
:
30: 30 minutes (Max)

13.3.45 Page 0: Register 52 (address = 0x34) [reset = 0x00]

SIGDET_SCAN_TIME is the alternate name for this register.

Figure 120. Page 0: Register 52
7 6 5 4 3 2 1 0
RSV TIME
R/W-0 0000b R/W-000b

Table 70. Page 0: Register 52 Field Descriptions

Bit Field Type Reset Description
7-33 RSV R/W 0 0000 Reserved. Do not access.
2-1 TIME R/W 000 Configures the scan time for each channel in the SLEEP state
000: 160 ms (default)
001: 80 ms
010: 40 ms
011: 20 ms
100: 10 ms
Others: Invalid

13.3.46 Page 0: Register 54 (address = 0x36) [reset = 0x01]

SIGDET_INT_INTVL is the alternate for this register.

Figure 121. Page 0: Register 54
7 6 5 4 3 2 1 0
RSV RSV RSV RSV RSV INT_INTVL
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-1b

Table 71. Page 0: Register 54 Field Descriptions

Bit Field Type Reset Description
7-3 RSV R/W 0 0000 Reserved. Do not access.
2-0 INT_INTVL R/W 001b Interval time of the signal detector interrupt when there is signal detection. This time value is used for energysense wakeup from sleep interrupt and from controlsense interrupts
Interval time of the signal-resume interrupt
000: No repeat
001: 1 sec (default)
010: 2 sec
011: 3 sec
100: 4 sec
Others: Invalid

13.3.47 Page 0: Register 64 (address = 0x40) [reset =0x80]

SIGDET_DC_REF_CH1_L is the alternate name for this register.

Figure 122. Page 0: Register 64
7 6 5 4 3 2 1 0
REF
R/W-1000 0000b

Table 72. Page 0: Register 64 Field Descriptions

Bit Field Type Reset Description
7-0 REF R/W 1000 0000b Reference Level of Controlsense Detection

13.3.48 Page 0: Register 65 (address = 0x41) [reset = 0x7F]

SIGDET_DC_DIFF_CH1_L is the alternate name for this register.

Figure 123. Page 0: Register 65
7 6 5 4 3 2 1 0
DIFF
R/W-0111 1111b

Table 73. Page 0: Register 65 Field Descriptions

Bit Field Type Reset Description
7-0 DIFF R/W 0111 1111b Difference Level of Controlsense Detection

13.3.49 Page 0: Register 66 (address = 0x42) [reset = 0x00]

SIGDET_DC_LEVEL_CH1_L is the alternate name for this register.

Figure 124. Page 0: Register 66
7 6 5 4 3 2 1 0
LEVEL
R-0000 0000b

Table 74. Page 0: Register 66 Field Descriptions

Bit Field Type Reset Description
7-0 LEVEL R 0000 0000b Current DC Level

13.3.50 Page 0: Register 67 (address = 0x43) [reset = 0x80]

SIGDET_DC_REF_CH1_R is the alternate name for this register.

Figure 125. Page 0: Register 67
7 6 5 4 3 2 1 0
REF
R/W-1000 0000b

Table 75. Page 0: Register 67 Field Descriptions

Bit Field Type Reset Description
7-0 REF R/W 1000 0000b Reference Level of Controlsense Detection

13.3.51 Page 0: Register 68 (address = 0x44) [reset = 0x7F]

SIGDET_DC_DIFF_CH1_R is the alternate name for this register.

Figure 126. Page 0: Register 68
7 6 5 4 3 2 1 0
DIFF
R/W-0111 1111b

Table 76. Page 0: Register 68 Field Descriptions

Bit Field Type Reset Description
7-0 DIFF R/W 0111 1111b Difference Level of Controlsense Detection

13.3.52 Page 0: Register 69 (address = 0x45) [reset = 0x00]

SIGDET_DC_LEVEL_CH 1_R is the alternate name for this register.

Figure 127. Page 0: Register 69
7 6 5 4 3 2 1 0
LEVEL
R-0000 0000b

Table 77. Page 0: Register 69 Field Descriptions

Bit Field Type Reset Description
7-0 LEVEL R 0000 0000b Current DC Level

13.3.53 Page 0: Register 70 (address = 0x46) [reset = 0x80]

SIGDET_DC_REF_CH2_L is the alternate name for this register.

Figure 128. Page 0: Register 70
7 6 5 4 3 2 1 0
REF
R/W-1000 0000b

Table 78. Page 0: Register 70 Field Descriptions

Bit Field Type Reset Description
7-0 REF R/W 1000 0000b Reference Level of Controlsense Detection

13.3.54 Page 0: Register 71 (address = 0x47) [reset = 0x7F]

SIGDET_DC_DIFF_CH2_L is the alternate name for this register.

Figure 129. Page 0: Register 71
7 6 5 4 3 2 1 0
DIFF
R/W-0111 1111b

Table 79. Page 0: Register 71 Field Descriptions

Bit Field Type Reset Description
7-0 DIFF R/W 0111 1111b Difference Level of Controlsense Detection

13.3.55 Page 0: Register 72 (address = 0x48) [reset = 0x00]

SIGDET_DC_LEVEL_CH2_L is the alternate name for this register.

Figure 130. Page 0: Register 72
7 6 5 4 3 2 1 0
LEVEL
R-0000 0000b

Table 80. Page 0: Register 72 Field Descriptions

Bit Field Type Reset Description
7-0 LEVEL R 0000 0000b Current DC Level

13.3.56 Page 0: Register 73 (address = 0x49) [reset = 0x80]

SIGDET_DC_REF_CH2_R is the alternate name for this register.

Figure 131. Page 0: Register 73
7 6 5 4 3 2 1 0
REF
R/W-1000 0000b

Table 81. Page 0: Register 73 Field Descriptions

Bit Field Type Reset Description
7-0 REF R/W 1000 0000b Reference Level of Controlsense Detection

13.3.57 Page 0: Register 74 (address = 0x4A) [reset = 0x7F]

SIGDET_DC_DIFF_CH2_R is the alternate name for this register.

Figure 132. Page 0: Register 74
7 6 5 4 3 2 1 0
DIFF
R/W-0111 1111b

Table 82. Page 0: Register 74 Field Descriptions

Bit Field Type Reset Description
7-0 DIFF R/W 0111 1111b Difference Level of Controlsense Detection

13.3.58 Page 0: Register 75 (address = 0x4B) [reset = 0x00]

SIGDET_DC_LEVEL_CH 2_R is the alternate name for this register.

Figure 133. Page 0: Register 75
7 6 5 4 3 2 1 0
LEVEL
R-0000 0000b

Table 83. Page 0: Register 75 Field Descriptions

Bit Field Type Reset Description
7-0 LEVEL R 0000 0000b Current DC Level

13.3.59 Page 0: Register 76 (address = 0x4C) [reset = 0x80]

SIGDET_DC_REF_CH3_L is the alternate name for this register.

Figure 134. Page 0: Register 76
7 6 5 4 3 2 1 0
REF
R/W-1000 0000b

Table 84. Page 0: Register 76 Field Descriptions

Bit Field Type Reset Description
7-0 REF R/W 1000 0000b Reference Level of Controlsense Detection

13.3.60 Page 0: Register 77 (address = 0x4D) [reset = 0x7F]

SIGDET_DC_DIFF_CH3_L is the alternate name for this register.

Figure 135. Page 0: Register 77
7 6 5 4 3 2 1 0
DIFF
R/W-0111 1111b

Table 85. Page 0: Register 77 Field Descriptions

Bit Field Type Reset Description
7-0 DIFF R/W 0111 1111b Difference Level of Controlsense Detection

13.3.61 Page 0: Register 78 (address = 0x4E) [reset = 0x00]

SIGDET_DC_LEVEL_CH3_L is the alternate name for this register.

Figure 136. Page 0: Register 78
7 6 5 4 3 2 1 0
LEVEL
R-0000 0000b

Table 86. Page 0: Register 78 Field Descriptions

Bit Field Type Reset Description
7-0 LEVEL R 0000 0000b Current DC Level

13.3.62 Page 0: Register 79 (address = 0x4F) [reset = 0x80]

SIGDET_DC_REF_CH3_R is the alternate name for this register.

Figure 137. Page 0: Register 79
7 6 5 4 3 2 1 0
REF
R/W-1000 0000b

Table 87. Page 0: Register 79 Field Descriptions

Bit Field Type Reset Description
7-0 REF R/W 1000 0000b Reference Level of Controlsense Detection

13.3.63 Page 0: Register 80 (address = 0x50) [reset = 0x7F]

SIGDET_DC_DIFF_CH3_R is the alternate name for this register.

Figure 138. Page 0: Register 80
7 6 5 4 3 2 1 0
DIFF
R/W-0111 1111b

Table 88. Page 0: Register 80 Field Descriptions

Bit Field Type Reset Description
7-0 DIFF R/W 0111 1111b Difference Level of Controlsense Detection

13.3.64 Page 0: Register 81 (address = 0x51) [reset = 0x00]

SIGDET_DC_LEVEL_CH3_R is the alternate name for this register.

Figure 139. Page 0: Register 81
7 6 5 4 3 2 1 0
LEVEL
R-0000 0000b

Table 89. Page 0: Register 81 Field Descriptions

Bit Field Type Reset Description
7-0 LEVEL R 0000 0000b Current DC Level

13.3.65 Page 0: Register 82 (address = 0x52) [reset = 0x80]

SIGDET_DC_REF_CH4_L is the alternate name for this register.

Figure 140. Page 0: Register 82
7 6 5 4 3 2 1 0
REF
R/W-1000 0000b

Table 90. Page 0: Register 82 Field Descriptions

Bit Field Type Reset Description
7-0 REF R/W 1000 0000b Reference Level of Controlsense Detection

13.3.66 Page 0: Register 83 (address = 0x53) [reset = 0x7F]

SIGDET_DC_DIFF_CH4_L is the alternate name for this register.

Figure 141. Page 0: Register 83
7 6 5 4 3 2 1 0
DIFF
R/W-0111 1111b

Table 91. Page 0: Register 83 Field Descriptions

Bit Field Type Reset Description
7-0 DIFF R/W 0111 1111b Difference Level of Controlsense Detection

13.3.67 Page 0: Register 84 (address = 0x54) [reset = 0x00]

SIGDET_DC_LEVEL_CH4_L is the alternate name for this register.

Figure 142. Page 0: Register 84
7 6 5 4 3 2 1 0
LEVEL
R-0000 0000b

Table 92. Page 0: Register 84 Field Descriptions

Bit Field Type Reset Description
7-0 LEVEL R 0000 0000b Current DC Level

13.3.68 Page 0: Register 85 (address = 0x55) [reset = 0x80]

SIGDET_DC_REF_CH4_R is the alternate name for this register.

Figure 143. Page 0: Register 82
7 6 5 4 3 2 1 0
REF
R/W-1000 0000b

Table 93. Page 0: Register 85 Field Descriptions

Bit Field Type Reset Description
7-0 REF R/W 1000 0000b Reference Level of Controlsense Detection

13.3.69 Page 0: Register 86 (address = 0x56) [reset = 0x7F]

SIGDET_DC_DIFF_CH4_R is the alternate name for this register.

Figure 144. Page 0: Register 86
7 6 5 4 3 2 1 0
DIFF
R/W-0111 1111b

Table 94. Page 0: Register 86 Field Descriptions

Bit Field Type Reset Description
7-0 DIFF R/W 0111 1111b Difference Level of Controlsense Detection

13.3.70 Page 0: Register 87 (address = 0x57) [reset = 0x00]

Figure 145. Page 0: Register 84
7 6 5 4 3 2 1 0
LEVEL
R-0000 0000b

Table 95. Page 0: Register 87 Field Descriptions

Bit Field Type Reset Description
7-0 LEVEL R 0000 0000b Current DC Level

13.3.71 Page 0: Register 88 (address = 0x58) [reset = 0x00]

AUXADC_DATA_CTRL is the alternate name for this register.

Figure 146. Page 0: Register 88
7 6 5 4 3 2 1 0
DC_NOLATCH AUXADC_RDY DC_RDY AUXADC_LATCH AUXADC_DATA_TYPE DC_CH
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-000b

Table 96. Page 0: Register 88 Field Descriptions

Bit Field Type Reset Description
7 DC_NOLATCH R/W 0b Read Without Latch
Read directly without latch operation (from secondary ADC)
0: With latch operation (default)
1: Without latch operation when read dc value
6 AUXADC_RDY R/W 0b AUXADC Ready
Indicate latch operation is finished and AUXADC value is ready for read operation.
0: Latch operation is running (default)
1: AUXADC value is ready for read operation
5 DC_RDY R/W 0b DC Ready
Indicate latch operation is finished and dc value is ready.
0: Latch operation is running (default)
1: DC value is ready for read operation
4 AUXADC_LATCH R/W 0b AUXADC Latch
Trigger to latch 16-bit AUXADC value for read operation: rising edge is the trigger signal
0: Idle (default)
1: Latch the value for read operation
3 AUXADC_DATA_TYPE R/W 0b Data to be Read From Control Interface
0: read LPF data (default)
1: read HPF data
2-0 DC_CH[2:0] R/W 000b DC-Value Channel Select
Select dc-value channel to be latched for control-interface read operation
000: CH1_L (default)
001: CH1_R
010: CH2_L
011: CH2_R
100: CH3_L
101: CH3_R
110: CH4_L
111: CH4_R

13.3.72 Page 0: Register 89 (address = 0x59) [reset = 0x00]

Figure 147. Page 0: Register 89
7 6 5 4 3 2 1 0
AUXADC_DATA_LSB
R-0000 0000b

Table 97. Page 0: Register 89 Field Descriptions

Bit Field Type Reset Description
7-0 AUXADC_DATA_LSB R 0000 0000b Low Byte of Secondary ADC Output
The data depends on AUXADC_DATA_TYPE setting AUXADC_DATA_TYPE = 0: reading LPF of secondary ADC AUXADC_DATA_TYPE = 1: reading HPF of secondary ADC

13.3.73 Page 0: Register 90 (address = 0x5A) [reset = 0x00]

Figure 148. Page 0: Register 90
7 6 5 4 3 2 1 0
AUXADC_DATA_MSB
R-0000 0000b

Table 98. Page 0: Register 90 Field Descriptions

Bit Field Type Reset Description
7-0 AUXADC_DATA_MSB R 0000 0000b High Byte of Secondary ADC Output [15:8]
The data depends on AUXADC_DATA_TYPE setting AUXADC_DATA_TYPE = 0: reading LPF of secondary ADC AUXADC_DATA_TYPE = 1: reading HPF of secondary ADC

13.3.74 Page 0: Register 96 (address = 0x60) [reset = 0x01]

Figure 149. Page 0: Register 96
7 6 5 4 3 2 1 0
RSV POSTPGA_CP RSV DC_CHANG DIN_TOGGLE ENGSTR
R/W-000b R/W-0b R/W-0b R/W-0b R/W-0b R/W-1b

Table 99. Page 0: Register 96 Field Descriptions

Bit Field Type Reset Description
7-5 RSV R/W 000b Reserved. Always write 000b.
4 POSTPGA_CP R/W 0b Enable the Post-PGA Clipping Interrupt
Write 0 to clear interrupts, all bits in this register
0: Disable (default)
1: Enable
3 RSV R/W 0b Reserved. Always write 0b.
2 DC_CHANG R/W 0b Enable the DC Level Change Interrupt
0: Disable (default)
1: Enable
1 DIN_TOGGLE R/W 0b Enable I2S RX DIN toggle Interrupt
0: Disable (default)
1: Enable
0 ENGSTR R/W 1b Enable the energysense Interrupt
0: Disable
1: Enable (default)

13.3.75 Page 0: Register 97 (address = 0x61) [reset = 0x00]

Figure 150. Page 0: Register 97
7 6 5 4 3 2 1 0
RSV POSTPGA_CP RSV DC_CHANG DIN_TOGGLE ENGSTR
R-000b R-0b R-0b R-0b R-0b R-0b

Table 100. Page 0: Register 97 Field Descriptions

Bit Field Type Reset Description
7-5 RSV R 000b Reserved. Always write 000b.
4 POSTPGA_CP R 0b Status of Post-PGA Clipping Interrupt
Write 0 to register 0x60 clear interrupts, all bits in this register
0: None
1: Interrupt occurred
3 RSV R 0b Reserved. Always write 0b.
2 DC_CHANG R 0b Status of the DC Level Change Interrupt
0: None
1: Interrupt occurred
1 DIN_TOGGLE R 0b Status of I2S RX DIN toggle Interrupt
0: None
1: Interrupt occurred
0 ENGSTR R 0b Status of the energysense Interrupt
0: None
1: Interrupt occurred

13.3.76 Page 0: Register 98 (address = 0x62) [reset =0x10]

Figure 151. Page 0: Register 98
7 6 5 4 3 2 1 0
RSV POL RSV WIDTH
R/W-00b R/W-01b R/W-00b R/W-00b

Table 101. Page 0: Register 98 Field Descriptions

Bit Field Type Reset Description
7-5 RSV R/W 00b Reserved. Always write 00b.
5-4 POL R/W 01b Polarity of the Interrupt Pulse
00: Low active
01: High active (default)
10: Open drain (L-Active)
11: Reserved
3-2 RSV R/W 00b Reserved. Always write 00b.
1-0 WIDTH R/W 00b Width of the Interrupt Pulse
00: 1 ms (default)
01: 2 ms
10: 3 ms
11: Infinity for level sense

13.3.77 Page 0: Register 112 (address = 0x70) [reset = 0x70]

Figure 152. Page 0: Register 112
7 6 5 4 3 2 1 0
RSV PWRDN SLEEP STBY
R/W-0 1110b R/W-0b R/W-0b R/W-0b

Table 102. Page 0: Register 112 Field Descriptions

Bit Field Type Reset Description
7-3 RSV R/w 0 1110b Reserved. Always write 0 1110b
2 PWRDN R/W 0b Enter Analog Power Down State
0: Power Up (default)
1: Power Down
1 SLEEP R/W 0b Enter the Device Sleep State
After the chip enters SLEEP state, energysense application will be triggered.
0: Power Up (default)
1: Sleep
0 STBY R/W 0b Enter Digital Standby State
0: Run (default)
1: Standby

13.3.78 Page 0: Register 113 (address = 0x71) [reset = 0x10]

DSP_CTRL is the alternate name for this register.

Figure 153. Page 0: Register 113
7 6 5 4 3 2 1 0
2CH RSV FLT HPF_EN MUTE_CH2_R MUTE_CH2_L MUTE_CH1_R MUTE_CH1_L
R/W-0b R/W-0b R/W-0b R/W-1b R/W-0b R/W-0b R/W-0b R/W-0b

Table 103. Page 0: Register 113 Field Descriptions

Bit Field Type Reset Description
7 2CH R/W 0b Processing Mode Selection
Select the processing mode for 4-channel device only. This configuration CANNOT be changed on the fly in RUN state.
0: 4 channels (default)
1: 2 channels
6 RSV R/W 0b Reserved. Always write 0b.
5 FLT R/W 0b Select Decimation Filter Type
0: Normal (default)
1: Short latency
4 HPF_EN R/W 1b Enable High-Pass Filter
0: Disable
1: Enable (default)
3 MUTE_CH2_R R/W 0b Mute Ch2(R)
0: Unmute (default)
1: Mute
2 MUTE_CH2_L R/W 0b Mute Ch2(L)
0: Unmute (default)
1: Mute
1 MUTE_CH1_R R/W 0b Mute Ch1(R)
0: Unmute (default)
1: Mute
0 MUTE_CH1_L R/W 0b Mute Ch1(L)
0: Unmute (default)
1: Mute

13.3.79 Page 0: Register 114 (address = 0x72) [reset = 0x00]

Figure 154. Page 0: Register 114
7 6 5 4 3 2 1 0
RSV STATE
R-0000b R-0000b

Table 104. Page 0: Register 114 Field Descriptions

Bit Field Type Reset Description
7-4 RSV R 0000b Reserved. Always write 0000b.
3-0 STATE R 0000b Device Current Status
0000: Power down (default)
0001: Wait clock stable
0010: Release reset
0011: Stand-by
0100: Fade IN
0101: Fade OUT
0110: Reserved
0111: Reserved
1000: Reserved
1001: Sleep
1010: Reserved
1011: Reserved
1100: Reserved
1101: Reserved
1110: Reserved
1111: Run

13.3.80 Page 0: Register 115 (address = 0x73) [reset = 0x00]

Figure 155. Page 0: Register 115
7 6 5 4 3 2 1 0
RSV INFO
R-0 0000b R-000b

Table 105. Page 0: Register 115 Field Descriptions

Bit Field Type Reset Description
7-3 RSV R 0 0000b Reserved. Always write 0 0000b.
2-0 INFO R 000b Current Sampling Frequency
000: Out of range (Low) or LRCK Halt (default)
001: 8 kHz
010: 16 kHz
011: 32 khz to 48 kHz
100: 88.2 kHz to 96 kHz
101: 176.4 kHz to 192 kHz
110: Out of range (High)
111: Invalid fS

13.3.81 Page 0: Register 116 (address = 0x74) [reset = 0x00]

Figure 156. Page 0: Register 116
7 6 5 4 3 2 1 0
RSV BCK_RATIO RSV SCK_RATIO
R-0b R-000b R-0b R-000b

Table 106. Page 0: Register 116 Field Descriptions

Bit Field Type Reset Description
7 RSV R 0b Reserved. Always write 0 0000b.
6-4 BCK_RATIO R 000b Current Receiving BCK Ratio
Default value: 000 (default)
000: Out of range (L) or BCK Halt
001: 32
010: 48
011: 64
100: 256
101: (Not assigned)
110: Out of range (H)
111: Invalid BCK ratio or LRCK Halt
3 RSV R 0b Reserved. Always write 0 0000b.
2-0 SCK_RATIO R 000b Current SCK Ratio
000: Out of range (L) or SCK Halt (default)
001: 128
010: 256
011: 384
100: 512
101: 768
110: Out of range (H)
111: Invalid SCK ratio or LRCK Halt

13.3.82 Page 0: Register 117 (address = 0x75) [reset = 0x00]

CLK_ERR_STAT is the alternate name for this register.

Figure 157. Page 0: Register 117
7 6 5 4 3 2 1 0
RSV LRCKHLT BCKHLT SCKHTL RSV LRCKERR BCKERR SCKERR
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b

Table 107. Page 0: Register 117 Field Descriptions

Bit Field Type Reset Description
7 RSV R 0b Reserved. Always write 0b.
6 LRCKHLT R 0b LRCK Halt Status
0: No Error (default)
1: Halt
5 BCKHLT R 0b BCK Halt Status
0: No Error (default)
1: Halt
4 SCKHTL R 0b SCK Halt Status
0: No Error (default)
1: Halt
3 RSV R 0b Reserved. Always write 0b.
2 LRCKERR R 0b LRCK Error Status
0: No Error (default)
1: Error
1 BCKERR R 0b BCK Error Status
0: No Error (default)
1: Error
0 SCKERR R 0b SCK Error Status
0: No Error (default)
1: Error

13.3.83 Page 0: Register 120 (address = 0x78) [reset = 0x00]

Figure 158. Page 0: Register 120
7 6 5 4 3 2 1 0
RSV DVDD AVDD LDO
R/W-0b R/W-0b R/W-0b R/W-0b

Table 108. Page 0: Register 120 Field Descriptions

Bit Field Type Reset Description
7-3 RSV R 0 0000b Reserved. Always write 0 0000b.
2 DVDD R 0b DVDD Status
0:Bad or Missing (default)
1:Good
1 AVDD R 0b AVDD Status
0:Bad or issing (default)
1:Good
0 LDO R 0b Digital LDO Status
0:Bad or Missing (default)
1:Good

13.4 Page 1 Registers

13.4.1 Page 1: Register 1 (address = 0x01) [reset = 0x00]

Figure 159. Page 1: Register 1
7 6 5 4 3 2 1 0
RSV DONE RSV BUSY R_REQ W_REQ
R/W-000b R-0b R/W-0b R-0b R/W-0b R/W-0b

Table 109. Page 1: Register 1 Field Descriptions

Bit Field Type Reset Description
7-5 RSV R/W 000b Reserved. Always write 000b.
4 DONE R 0b Done Status Flag
1: Write or read operation is done with one cycle as indicator
0: Idle or is busy (default)
3 RSV R/W 0b Reserved. Always write 000b.
2 BUSY R 0b Busy Status Flag
1: Write or read operation is running and not finished
0: Write or read operation is finished (default)
1 R_REQ R/W 0b Memory Mapper Register Access to DSP-2 - READ
1: Request read operation
0: The read operation is done and data is ready to read from I2C/SPI interface (default)
0 W_REQ R/W 0b Memory Mapper Register Access to DSP-2 - WRITE
1: Request write operation
0: The write operation is done and is ready for next write operation command (default)

13.4.2 Page 1: Register 2 (address = 0x02) [reset = 0x00]

Figure 160. Page 1: Register 2
7 6 5 4 3 2 1 0
RSV MEM_ADDR
R/W-0b R/W-000 0000b

Table 110. Page 1: Register 2 Field Descriptions

Bit Field Type Reset Description
7 RSV R/W 0b Reserved. Always write 0b.
6-0 MEM_ADDR R/W 000 0000b Memory Mapped Register Address
Status of the memory mapped register access

13.4.3 Page 1: Register 4 (address = 0x04) [reset = 0x00]

Figure 161. Page 1: Register 4
7 6 5 4 3 2 1 0
MEM_WDATA_0
R/W-0000 0000b

Table 111. Page 1: Register 4 Field Descriptions

Bit Field Type Reset Description
7-0 MEM_WDATA_0 R/W 0000 0000b Write Data to 24-Bit Memory
Coefficient [23:16]

13.4.4 Page 1: Register 5 (address = 0x05) [reset = 0x00]

Figure 162. Page 1: Register 5
7 6 5 4 3 2 1 0
MEM_WDATA_1
R/W-0000 0000b

Table 112. Page 1: Register 5 Field Descriptions

Bit Field Type Reset Description
7-0 MEM_WDATA_1 R/W 0000 0000b Write Data to 24-Bit Memory
Coefficient [15:8]

13.4.5 Page 1: Register 6 (address = 0x06) [reset = 0x00]

Figure 163. Page 1: Register 6
7 6 5 4 3 2 1 0
MEM_WDATA_2
R/W-0000 0000b

Table 113. Page 1: Register 6 Field Descriptions

Bit Field Type Reset Description
7-0 MEM_WDATA_2 R/W 0000 0000b Write Data to 24-Bit Memory
Coefficient [7:0]

13.4.6 Page 1: Register 7 (address = 0x07) [reset = 0x00]

Figure 164. Page 1: Register 7
7 6 5 4 3 2 1 0
MEM_WDATA_3 RSV
R/W-0b R/W-000 0000b

Table 114. Page 1: Register 7 Field Descriptions

Bit Field Type Reset Description
7 MEM_WDATA_2 R/W 0b Write Data to 24-Bit Memory
Reserved
6-0 RSV R/W 000 0000b Reserved. Always write 000 0000b.

13.4.7 Page 1: Register 8 (address = 0x08) [reset = 0x00]

Figure 165. Page 1: Register 8
7 6 5 4 3 2 1 0
MEM_RDATA_0
R-0000 0000b

Table 115. Page 1: Register 8 Field Descriptions

Bit Field Type Reset Description
7-0 MEM_RDATA_0 R 0000 0000b Read Data from 24-Bit Memory
Coefficient [23:16]

13.4.8 Page 1: Register 9 (address = 0x09) [reset = 0x00]

Figure 166. Page 1: Register 9
7 6 5 4 3 2 1 0
MEM_RDATA_1
R-0000 0000b

Table 116. Page 1: Register 9 Field Descriptions

Bit Field Type Reset Description
7-0 MEM_RDATA_1 R 0000 0000b Read Data from 24-Bit Memory
Coefficient [15:8]

13.4.9 Page 1: Register 10 (address = 0x0A) [reset = 0x00]

Figure 167. Page 1: Register 10
7 6 5 4 3 2 1 0
MEM_RDATA_2
R-0000 0000b

Table 117. Page 1: Register 10 Field Descriptions

Bit Field Type Reset Description
7-0 MEM_RDATA_2 R 0000 0000b Read Data from 24-Bit Memory
Coefficient [7:0]

13.4.10 Page 1: Register 11 (address = 0x0B) [reset = 0x00]

Figure 168. Page 1: Register 11
7 6 5 4 3 2 1 0
MEM_RDATA_3 RSV
R/W-0b R/W-000 0000b

Table 118. Page 1: Register 11 Field Descriptions

Bit Field Type Reset Description
7 MEM_RDATA_3 R 0b Read Data from 24-Bit Memory
Reserved
6-0 RSV R/W 000 0000b Reserved. Always write 000 0000b.

13.5 Page 3 Registers

13.5.1 Page 3: Register 18 (address = 0x12) [reset =0x40]

Figure 169. Page 3: Register 18
7 6 5 4 3 2 1 0
RSV PD
R/W-010 0000b R/W-0b

Table 119. Page 3: Register 18 Field Descriptions

Bit Field Type Reset Description
7-1 RSV R/W 010 0000b Reserved. Always write 010 0000b
0 PD R/W 0b Oscillator Power Down Control
0: Power up (default)
1: Power down

13.5.2 Page 3: Register 21 (address = 0x15) [reset = 0x01]

Figure 170. Page 3: Register 21
7 6 5 4 3 2 1 0
RSV TERM RSV PDZ
R/W-000b W-0b R/W-000b W-1b

Table 120. Page 3: Register 21 Field Descriptions

Bit Field Type Reset Description
7-5 RSV R/W 000b Reserved. Always write 000b.
4 TERM W 0b Mic Bias Resistor Bypass (Write only)
0: Disable (default)
1: Enable
3-1 RSV R/W 000b Reserved. Always write 000b.
0 PDZ W 0b Mic Bias Control (Write only)
0: Power down
1: Power up (default)

13.6 Page 253 Registers

13.6.1 Page 253: Register 20 (address = 0x14) [reset = 0x00]

Figure 171. Page 253: Register 20
7 6 5 4 3 2 1 0
PGA_ICI REF_ICI RSV
R/W-00b R/W-00b R/W-0000b

Table 121. Page 253: Register 20 Field Descriptions

Bit Field Type Reset Description
7-6 PGA_ICI R/W 00b PGA Bias Current Trim
00: 100% (default)
01: Reserved
10: 75%
11: Reserved
5-4 REF_ICI R/W 00b Global bias current trim
00: 100% (default)
01: 75%
10: Reserved
11: Reserved
3-0 RSV R/W 0000b Reserved. Always write 0000b.