SLASE64A December 2014  – June 2017 PCM1860-Q1 , PCM1861-Q1 , PCM1862-Q1 , PCM1863-Q1 , PCM1864-Q1 , PCM1865-Q1

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: PGA and ADC AC Performance
    6. 7.6 Electrical Characteristics: DC
    7. 7.7 Electrical Characteristics: Digital Filter
    8. 7.8 Timing Requirements: External Clock
    9. 7.9 Timing Requirements: I2C Control Interface
    10. 7.10Timing Requirements: SPI Control Interface
    11. 7.11Timing Requirements: Audio Data Interface for Slave Mode
    12. 7.12Timing Requirements: Audio Data Interface for Master Mode
    13. 7.13Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagrams
    3. 9.3Features Description
      1. 9.3.1 Analog Front End
      2. 9.3.2 Microphone Support
        1. 9.3.2.1Mic Bias
      3. 9.3.3 Input Multiplexer (PCM1860-Q1 and PCM1861-Q1)
      4. 9.3.4 Mixers and Multiplexers (PCM1862-Q1, PCM1863-Q1, PCM1864-Q1, and PCM1865-Q1)
      5. 9.3.5 Programmable Gain Amplifier
      6. 9.3.6 Automatic Clipping Suppression
        1. 9.3.6.1Attenuation Level
        2. 9.3.6.2Channel Linking
      7. 9.3.7 Zero Crossing Detect
      8. 9.3.8 Digital Inputs
        1. 9.3.8.1Stereo PCM Sources
        2. 9.3.8.2Digital PDM Microphones
      9. 9.3.9 Clocks
        1. 9.3.9.1Description
        2. 9.3.9.2External Clock-Source Limits
        3. 9.3.9.3Device Clock Distribution and Generation
        4. 9.3.9.4Clocking Modes
          1. 9.3.9.4.1Clock Configuration and Selection for Hardware-Controlled Devices
          2. 9.3.9.4.2Clock Sources for Software-Controlled Devices
          3. 9.3.9.4.3Clocking Configuration and Selection for Software-Controlled Devices
            1. 9.3.9.4.3.1Target Clock Rates for ADC, DSP1 and DSP2
            2. 9.3.9.4.3.2Configuration of Master Mode
          4. 9.3.9.4.4BCK Input Slave PLL Mode
          5. 9.3.9.4.5Software-Controlled Devices ADC Non-Audio MCK PLL Mode
        5. 9.3.9.5Software-Controlled Devices Manual PLL Calculation
        6. 9.3.9.6Clock Halt and Error
        7. 9.3.9.7Clock Halt and Error Detect
        8. 9.3.9.8Changes in Clock Sources and Sample Rates
      10. 9.3.10Analog-to-Digital Converters (ADCs)
        1. 9.3.10.1Main Audio ADCs
        2. 9.3.10.2Secondary ADC: Energysense and Analog Control
          1. 9.3.10.2.1Secondary ADC Analog Input Range
          2. 9.3.10.2.2Frequency Response of the Secondary ADC
        3. 9.3.10.3Secondary ADC Controlsense DC Level Change Detection
      11. 9.3.11Energysense
        1. 9.3.11.1Energysense Signal Loss Flag
        2. 9.3.11.2Energysense Signal Detect Circuitry
          1. 9.3.11.2.1Energysense Threshold Levels for Both Signal Loss and Signal Detect
        3. 9.3.11.3Programming Various Coefficients for Energysense
      12. 9.3.12Audio Processing
        1. 9.3.12.1DSP1 Processing Features
          1. 9.3.12.1.1Digital Decimation Filters
          2. 9.3.12.1.2Digital PGA
        2. 9.3.12.2DSP2 Processing Features
          1. 9.3.12.2.1Digital Mixing Function
      13. 9.3.13Fade-In and Fade-Out Functions
      14. 9.3.14Mappable GPIO Pins
      15. 9.3.15Interrupt Controller
        1. 9.3.15.1DIN Toggle Detection
        2. 9.3.15.2Clearing Interrupts
          1. 9.3.15.2.1Reset Energysense Loss (in Active Mode)
          2. 9.3.15.2.2Reset Energysense Detect (In Sleep Mode)
          3. 9.3.15.2.3Reset Controlsense (Active and Sleep Modes)
          4. 9.3.15.2.4Reset DIN Toggle (In Sleep Mode)
          5. 9.3.15.2.5Reset PGA Clipping (Active)
      16. 9.3.16Audio Format Selection and Timing Details
        1. 9.3.16.1Audio Format Selection
        2. 9.3.16.2Serial Audio Interface Timing Details
        3. 9.3.16.3Digital Audio Output 2 Configuration
        4. 9.3.16.4Time Division Multiplex (TDM Support)
        5. 9.3.16.5Decimation Filter Select
        6. 9.3.16.6Serial Audio Data Interface Configuration
    4. 9.4Device Functional Modes
      1. 9.4.1Power Mode Descriptions
        1. 9.4.1.1PCM1860-Q1 and PCM1861-Q1 Hardware Device Power Down Functions
          1. 9.4.1.1.1Enter Standby Mode (From Active Mode)
          2. 9.4.1.1.2Exit From Standby Mode Back to Active
          3. 9.4.1.1.3Enter or Exit Sleep or Energysense Mode to Active
        2. 9.4.1.2PCM186x-Q1 Software Device Power Down Functions
          1. 9.4.1.2.1Enter or Exit Stand-by Mode
          2. 9.4.1.2.2Enter Sleep Mode
          3. 9.4.1.2.3Exit Sleep Mode
        3. 9.4.1.3Bypassing the Internal LDO to Reduce Power Consumption
    5. 9.5Programming
      1. 9.5.1Control
        1. 9.5.1.1Hardware Control Configuration
        2. 9.5.1.2Software-Controlled Device Configuration
        3. 9.5.1.3SPI Interface
          1. 9.5.1.3.1Register Read and Write Operation
        4. 9.5.1.4I2C Interface
          1. 9.5.1.4.1Slave Address
          2. 9.5.1.4.2Packet Protocol
      2. 9.5.2Current Status Registers
      3. 9.5.3Real World Software Configuration using Energysense and Controlsense
        1. 9.5.3.1Active Mode Flow Diagram
        2. 9.5.3.2Basic Device Configuration
        3. 9.5.3.3Clear Energysense Interrupt
        4. 9.5.3.4Update System Settings
        5. 9.5.3.5Sleep Mode Flow Diagram
        6. 9.5.3.6Update Controlsense values in Sleep Mode
          1. 9.5.3.6.1Update System Settings
      4. 9.5.4 Programming and Register Reference
        1. 9.5.4.1Coefficient Data Formats
      5. 9.5.5Programming DSP Coefficients on Software-Controlled Devices
  10. 10Application and Implementation
    1. 10.1Application Information
      1. 10.1.1Device Control Method
        1. 10.1.1.1Hardware Control
        2. 10.1.1.2Software Control
          1. 10.1.1.2.1SPI Control
          2. 10.1.1.2.2I2C Control
      2. 10.1.2Power-Supply Options
        1. 10.1.2.13.3-V AVDD, DVDD, and IOVDD
        2. 10.1.2.23.3-V AVDD, DVDD, and 1.8-V IOVDD
      3. 10.1.3Master Clock Source
      4. 10.1.4Dual PCM186x-Q1 TDM Functionality
      5. 10.1.5Analog Input Configuration
        1. 10.1.5.1Analog Front-End Circuit For Single-Ended, Line-In Applications
        2. 10.1.5.2Analog Front-End Circuit for Differential, Line-In Applications
    2. 10.2Typical Applications
      1. 10.2.1Stereo Recording Application for PCM186x-Q1 Hardware-Controlled Devices in Master Mode
        1. 10.2.1.1Design Requirements
        2. 10.2.1.2Detailed Design Procedure
        3. 10.2.1.3Application Curves
      2. 10.2.2Stereo Recording Application for PCM186x-Q1 Software-Controlled Devices in Slave PLL Mode with 1.8-V IOVDD
        1. 10.2.2.1Design Requirements
        2. 10.2.2.2Detailed Design Procedure
        3. 10.2.2.3Application Curves
  11. 11Power Supply Recommendations
    1. 11.1Power-Supply Distribution and Requirements
    2. 11.21.8-V Support
    3. 11.3Brownout Conditions
    4. 11.4Power-Up Sequence
    5. 11.5Lowest Power-Down Modes
      1. 11.5.1Lowest Power In Standby Mode (AVDD = DVDD = IOVDD = 3.3 V)
      2. 11.5.2Lowest Power in Sleep or Energysense Mode (AVDD = DVDD = IOVDD = 3.3 V)
      3. 11.5.3Lower Power in Sleep or Energysense Mode (AVDD = DVDD 3.3 V and IOVDD = 1.8 V)
    6. 11.6Power-On Reset Sequencing Timing Diagram
    7. 11.7Power Connection Examples
      1. 11.7.13.3-V AVDD, DVDD, and IOVDD Example
      2. 11.7.23.3-V AVDD, DVDD With 1.8-V IOVDD Example for Lower-Power Applications
    8. 11.8Fade In
  12. 12Layout
    1. 12.1Layout Guidelines
      1. 12.1.1Grounding and System Partitioning
    2. 12.2Layout Example
  13. 13Register Map
    1. 13.1Register Map Description
    2. 13.2Register Map Summary
    3. 13.3 Page 0 Registers
      1. 13.3.1 Page 0: Register 1 (address = 0x01) [reset = 0x00]
      2. 13.3.2 Page 0: Register 2 (address = 0x02) [reset = 0x00]
      3. 13.3.3 Page 0: Register 3 (address = 0x03) [reset = 0x00]
      4. 13.3.4 Page 0: Register 4 (address = 0x04) [reset = 0x00]
      5. 13.3.5 Page 0: Register 5 (address = 0x05) [reset = 0x86]
      6. 13.3.6 Page 0: Register 6 (address = 0x06) [reset = 0x41]
      7. 13.3.7 Page 0: Register 7 (address = 0x07) [reset = 0x41]
      8. 13.3.8 Page 0: Register 8 (address = 0x08) [reset = 0x42]
      9. 13.3.9 Page 0: Register 9 (address = 0x09) [reset = 0x42]
      10. 13.3.10Page 0: Register 10 (address = 0x0A) [reset = 0x00]
      11. 13.3.11Page 0: Register 11 (address = 0x0B) [reset = 0x44]
      12. 13.3.12 Page 0: Register 12 (address = 0x0C) [reset = 0x00]
      13. 13.3.13Page 0: Register 13 (address = 0x0D) [reset = 0x00]
      14. 13.3.14Page 0: Register 14 (address = 0x0E) [reset = 0x00]
      15. 13.3.15Page 0: Register 15 (address = 0x0F) [reset = 0x00]
      16. 13.3.16Page 0: Register 16 (address = 0x10) [reset = 0x01]
      17. 13.3.17Page 0: Register 17 (address = 0x11) [reset = 0x20]
      18. 13.3.18Page 0: Register 18 (address = 0x12) [reset = 0x00]
      19. 13.3.19Page 0: Register 19 (address = 0x13) [reset = 0x00]
      20. 13.3.20Page 0: Register 20 (address = 0x14) [reset = 0x00]
      21. 13.3.21Page 0: Register 21 (address = 0x15) [reset = 0x00]
      22. 13.3.22Page 0: Register 22 (address = 0x16) [reset = 0x00]
      23. 13.3.23Page 0: Register 23 (address = 0x17) [reset = 0x00]
      24. 13.3.24Page 0: Register 24 (address = 0x18) [reset = 0x00]
      25. 13.3.25Page 0: Register 25 (address = 0x19) [reset = 0x00]
      26. 13.3.26Page 0: Register 26 (address = 0x1A) [reset = 0x00]
      27. 13.3.27Page 0: Register 27 (address = 0x1B) [reset = 0x00]
      28. 13.3.28Page 0: Register 32 (address = 0x20) [reset = 0x01]
      29. 13.3.29Page 0: Register 33 (address = 0x21) [reset = 0x00]
      30. 13.3.30Page 0: Register 34 (address = 0x22) [reset = 0x01]
      31. 13.3.31Page 0: Register 35 (address = 0x23) [reset = 0x03]
      32. 13.3.32Page 0: Register 37 (address = 0x25) [reset = 0x07]
      33. 13.3.33Page 0: Register 38 (address = 0x26) [reset = 0x03]
      34. 13.3.34Page 0: Register 39 (address = 0x27) [reset = 0x3F]
      35. 13.3.35Page 0: Register 40 (address = 0x28) [reset = 0x01]
      36. 13.3.36Page 0: Register 41 (address = 0x29) [reset = 0x00]
      37. 13.3.37Page 0: Register 42 (address = 0x2A) [reset = 0x00]
      38. 13.3.38Page 0: Register 43 (address = 0x2B) [reset = 0x01]
      39. 13.3.39Page 0: Register 44 (address = 0x2C) [reset = 0x00]
      40. 13.3.40Page 0: Register 45 (address = 0x2D) [reset = 0x00]
      41. 13.3.41Page 0: Register 48 (address = 0x30) [reset = 0x00]
      42. 13.3.42Page 0: Register 49 (address = 0x31) [reset = 0x00]
      43. 13.3.43Page 0: Register 50 (address = 0x32) [reset = 0x00]
      44. 13.3.44Page 0: Register 51 (address = 0x33) [reset = 0x00]
      45. 13.3.45Page 0: Register 52 (address = 0x34) [reset = 0x00]
      46. 13.3.46Page 0: Register 54 (address = 0x36) [reset = 0x01]
      47. 13.3.47Page 0: Register 64 (address = 0x40) [reset =0x80]
      48. 13.3.48Page 0: Register 65 (address = 0x41) [reset = 0x7F]
      49. 13.3.49Page 0: Register 66 (address = 0x42) [reset = 0x00]
      50. 13.3.50Page 0: Register 67 (address = 0x43) [reset = 0x80]
      51. 13.3.51Page 0: Register 68 (address = 0x44) [reset = 0x7F]
      52. 13.3.52Page 0: Register 69 (address = 0x45) [reset = 0x00]
      53. 13.3.53Page 0: Register 70 (address = 0x46) [reset = 0x80]
      54. 13.3.54Page 0: Register 71 (address = 0x47) [reset = 0x7F]
      55. 13.3.55Page 0: Register 72 (address = 0x48) [reset = 0x00]
      56. 13.3.56Page 0: Register 73 (address = 0x49) [reset = 0x80]
      57. 13.3.57Page 0: Register 74 (address = 0x4A) [reset = 0x7F]
      58. 13.3.58Page 0: Register 75 (address = 0x4B) [reset = 0x00]
      59. 13.3.59Page 0: Register 76 (address = 0x4C) [reset = 0x80]
      60. 13.3.60Page 0: Register 77 (address = 0x4D) [reset = 0x7F]
      61. 13.3.61Page 0: Register 78 (address = 0x4E) [reset = 0x00]
      62. 13.3.62Page 0: Register 79 (address = 0x4F) [reset = 0x80]
      63. 13.3.63Page 0: Register 80 (address = 0x50) [reset = 0x7F]
      64. 13.3.64Page 0: Register 81 (address = 0x51) [reset = 0x00]
      65. 13.3.65Page 0: Register 82 (address = 0x52) [reset = 0x80]
      66. 13.3.66Page 0: Register 83 (address = 0x53) [reset = 0x7F]
      67. 13.3.67Page 0: Register 84 (address = 0x54) [reset = 0x00]
      68. 13.3.68Page 0: Register 85 (address = 0x55) [reset = 0x80]
      69. 13.3.69Page 0: Register 86 (address = 0x56) [reset = 0x7F]
      70. 13.3.70Page 0: Register 87 (address = 0x57) [reset = 0x00]
      71. 13.3.71Page 0: Register 88 (address = 0x58) [reset = 0x00]
      72. 13.3.72Page 0: Register 89 (address = 0x59) [reset = 0x00]
      73. 13.3.73Page 0: Register 90 (address = 0x5A) [reset = 0x00]
      74. 13.3.74Page 0: Register 96 (address = 0x60) [reset = 0x01]
      75. 13.3.75Page 0: Register 97 (address = 0x61) [reset = 0x00]
      76. 13.3.76Page 0: Register 98 (address = 0x62) [reset =0x10]
      77. 13.3.77Page 0: Register 112 (address = 0x70) [reset = 0x70]
      78. 13.3.78Page 0: Register 113 (address = 0x71) [reset = 0x10]
      79. 13.3.79Page 0: Register 114 (address = 0x72) [reset = 0x00]
      80. 13.3.80Page 0: Register 115 (address = 0x73) [reset = 0x00]
      81. 13.3.81Page 0: Register 116 (address = 0x74) [reset = 0x00]
      82. 13.3.82Page 0: Register 117 (address = 0x75) [reset = 0x00]
      83. 13.3.83Page 0: Register 120 (address = 0x78) [reset = 0x00]
    4. 13.4 Page 1 Registers
      1. 13.4.1 Page 1: Register 1 (address = 0x01) [reset = 0x00]
      2. 13.4.2 Page 1: Register 2 (address = 0x02) [reset = 0x00]
      3. 13.4.3 Page 1: Register 4 (address = 0x04) [reset = 0x00]
      4. 13.4.4 Page 1: Register 5 (address = 0x05) [reset = 0x00]
      5. 13.4.5 Page 1: Register 6 (address = 0x06) [reset = 0x00]
      6. 13.4.6 Page 1: Register 7 (address = 0x07) [reset = 0x00]
      7. 13.4.7 Page 1: Register 8 (address = 0x08) [reset = 0x00]
      8. 13.4.8 Page 1: Register 9 (address = 0x09) [reset = 0x00]
      9. 13.4.9 Page 1: Register 10 (address = 0x0A) [reset = 0x00]
      10. 13.4.10Page 1: Register 11 (address = 0x0B) [reset = 0x00]
    5. 13.5 Page 3 Registers
      1. 13.5.1Page 3: Register 18 (address = 0x12) [reset =0x40]
      2. 13.5.2Page 3: Register 21 (address = 0x15) [reset = 0x01]
    6. 13.6 Page 253 Registers
      1. 13.6.1Page 253: Register 20 (address = 0x14) [reset = 0x00]
  14. 14Device and Documentation Support
    1. 14.1Development Support
    2. 14.2Related Links
    3. 14.3Receiving Notification of Documentation Updates
    4. 14.4Community Resources
    5. 14.5Trademarks
    6. 14.6Electrostatic Discharge Caution
    7. 14.7Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Features

  • AEC-Q100 Qualified for Automotive Applications
    • Temperature Grade 1: –40°C ≤ TA ≤ +125°C
    • HBM ESD Classification Level 2
    • CDM ESD Classification Level C5
  • High SNR Performance:
    • 110-dB SNR (PCM1861-Q1/63-Q1/65-Q1)
    • 103-dB SNR (PCM1860-Q1/62-Q1/64-Q1)
  • ADC Sample Rate (fS) = 8 kHz to 192 kHz
  • Up To Four Independent ADC Channels Available
  • Single-Ended, 2.1-VRMS Full-Scale (FS) Input
  • Differential, 4.2-VRMS FS Input
  • Hardware (HW) Control: PCM1860-Q1/61-Q1
  • Software (SW) Control (I2C or SPI):
    PCM1862-Q1/63-Q1/64-Q1/65-Q1
  • Support for Up To Four Digital Microphones
    (SW-Controlled Devices)
  • Programmable Gain Amplifier (PGA):
    • Fixed Gain: 0 dB, 12 dB, 32 dB
      (PCM1860-Q1/61-Q1)
    • SW-Controlled Gain: –12 dB to +32 dB
      (PCM1862-Q1/63-Q1/64-Q1/65-Q1)
  • Integrated High-Performance Audio PLL
  • Single 3.3-V Power-Supply Operation
  • Power Dissipation at 3.3 V:
    • < 85 mW (PCM1860-Q1/61-Q1/62-Q1/63-Q1)
    • < 145 mW (PCM1864-Q1/65-Q1)
  • Energysense Audio Content Detector for Auto System Wakeup and Sleep
  • Master or Slave Audio Interface
  • Automatic PGA Clipping Suppression Control
  • PCB-Footprint Compatibility Across All Devices

Applications

  • Automotive Head Units
  • External Car Amplifiers
  • Telematics Control Unit (TCU)

Description

The PCM186x-Q1 family (PCM1860-Q1, PCM1861-Q1, PCM1862-Q1, PCM1863-Q1, PCM1864-Q1, and PCM1865-Q1) of audio front-end devices take a new approach to audio-function integration to ease compliance with European Ecodesign legislation, while enabling high-performance end products at reduced cost. The PCM186x-Q1 support single-supply operation at 3.3 V, and offer an integrated programable gain amplifier (PGA) in a small package; this configuration makes it feasible to implement smaller and smarter products at a reduced cost.

The PCM186x-Q1 audio front end supports single-ended input levels from small-mV microphone inputs to 2.1-VRMS line inputs, without external resistor dividers. The front-end mixer (MIX), multiplexer (MUX), and PGA also support differential (Diff), pseudo-differential, and single-ended (SE) inputs, making these devices an ideal interface for products that require interference suppression. The PCM186x-Q1 integrate many system-level functions that assist or replace some DSP functions.

An integrated band-gap voltage reference provides excellent PSRR, so that a dedicated analog 3.3-V rail may not be required.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
PCM186x-Q1TSSOP (30)7.80 mm × 4.40 mm
  1. For all available packages, see the package option addendum at the end of the data sheet.

Simplified Application Diagram

PCM1860-Q1 PCM1861-Q1 PCM1862-Q1 PCM1863-Q1 PCM1864-Q1 PCM1865-Q1 pcm186x-simplified-application-diagram.gif