SLDS204A October 2014  – June 2016 PGA300

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Reverse Voltage Protection
    6. 6.6 Electrical Characteristics - Regulators
    7. 6.7 Electrical Characteristics - Internal Reference
    8. 6.8 Electrical Characteristics - Bridge Sensor Supply
    9. 6.9 Electrical Characteristics - Temperature Sensor Supply
    10. 6.10Electrical Characteristics - Internal Temperature Sensor
    11. 6.11Electrical Characteristics - P Gain (Chopper Stabilized)
    12. 6.12Electrical Characteristics - P Analog-to-Digital Converter
    13. 6.13Electrical Characteristics - T Gain (Chopper Stabilized)
    14. 6.14Electrical Characteristics - T Analog-to-Digital Converter
    15. 6.15Electrical Characteristics - One-Wire Interface
    16. 6.16Electrical Characteristics - DAC Output
    17. 6.17Electrical Characteristics - DAC Gain
    18. 6.18Electrical Characteristics - Non-Volatile Memory
    19. 6.19Electrical Characteristics - Diagnostics
    20. 6.20Operating Characteristics
    21. 6.21Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1 Reverse-Voltage Protection Block
      2. 7.3.2 Linear Regulators
      3. 7.3.3 Internal Reference
        1. 7.3.3.1High-Voltage Reference
        2. 7.3.3.2Accurate Reference
      4. 7.3.4 BRG+ to BRG- Supply for the Resistive Bridge
      5. 7.3.5 ITEMP Supply for the Temperature Sensor
      6. 7.3.6 Internal Temperature Sensor
      7. 7.3.7 P Gain
      8. 7.3.8 P Analog-to-Digital Converter
        1. 7.3.8.1P Sigma-Delta Modulator for P ADC
        2. 7.3.8.2P Decimation Filter for P ADC
      9. 7.3.9 T Gain
      10. 7.3.10T Analog-to-Digital Converter
        1. 7.3.10.1T Sigma-Delta Modulator for T ADC
        2. 7.3.10.2T Decimation Filters for T ADC
      11. 7.3.11P GAIN and T GAIN Calibration
      12. 7.3.12One-Wire Interface (OWI)
        1. 7.3.12.1Overview of OWI
        2. 7.3.12.2Activating and Deactivating the OWI Interface
          1. 7.3.12.2.1Activating OWI Communication
          2. 7.3.12.2.2Deactivating OWI Communication
        3. 7.3.12.3OWI Protocol
          1. 7.3.12.3.1OWI Frame Structure
            1. 7.3.12.3.1.1Standard Field Structure
            2. 7.3.12.3.1.2Frame Structure
            3. 7.3.12.3.1.3Sync Field
            4. 7.3.12.3.1.4Command Field
            5. 7.3.12.3.1.5Data Fields
          2. 7.3.12.3.2OWI Commands
            1. 7.3.12.3.2.1OWI Write Command
            2. 7.3.12.3.2.2OWI Read Initialization Command
            3. 7.3.12.3.2.3OWI Read-Response Command
            4. 7.3.12.3.2.4OWI Burst-Write Command (EEPROM Cache Access)
            5. 7.3.12.3.2.5OWI Burst Read Command (EEPROM Cache Access)
          3. 7.3.12.3.3OWI Operations
            1. 7.3.12.3.3.1Write Operation
            2. 7.3.12.3.3.2Read Operation
            3. 7.3.12.3.3.3EEPROM Burst Write
            4. 7.3.12.3.3.4EEPROM Burst Read
        4. 7.3.12.4OWI Communication-Error Status
      13. 7.3.13DAC Output
        1. 7.3.13.1Ratiometric vs Absolute
      14. 7.3.14DAC Gain
      15. 7.3.15Memory
        1. 7.3.15.1EEPROM Memory
          1. 7.3.15.1.1EEPROM Cache
          2. 7.3.15.1.2EEPROM Programming Procedure
          3. 7.3.15.1.3EEPROM Programming Current
          4. 7.3.15.1.4CRC
        2. 7.3.15.2Control and Status Registers Memory
      16. 7.3.16Diagnostics
        1. 7.3.16.1Power Supply Diagnostics
        2. 7.3.16.2Signal Chain Faults
          1. 7.3.16.2.1P Gain and T Gain Input Faults
          2. 7.3.16.2.2P Gain and T Gain Output Diagnostics
          3. 7.3.16.2.3Masking Signal Chain Faults
          4. 7.3.16.2.4Fault Detection Timing
      17. 7.3.17Digital Compensation and Filter
        1. 7.3.17.1Digital Gain and Offset
        2. 7.3.17.2TC and NL Correction
          1. 7.3.17.2.1TC and NL Coefficients
            1. 7.3.17.2.1.1No TC and NL Coefficients
          2. 7.3.17.2.2TC Compensation Using the Internal Temperature Sensor
        3. 7.3.17.3Clamping
        4. 7.3.17.4Filter
      18. 7.3.18Filter Coefficients
        1. 7.3.18.1No Filtering
        2. 7.3.18.2Filter Coefficients for P ADC Sampling Rate = 128 µs
    4. 7.4Device Functional Modes
      1. 7.4.1Voltage Mode
      2. 7.4.2Current Mode
    5. 7.5Register Maps
      1. 7.5.1Register Settings
      2. 7.5.2Control and Status Registers
        1. 7.5.2.1 DAC_CONFIG
        2. 7.5.2.2 OP_STAGE_CTRL
        3. 7.5.2.3 BRDG_CTRL
        4. 7.5.2.4 P_GAIN_SELECT
        5. 7.5.2.5 T_GAIN_SELECT
        6. 7.5.2.6 TEMP_CTRL
        7. 7.5.2.7 TEMP_SE
        8. 7.5.2.8 DIAG_ENABLE
        9. 7.5.2.9 AFEDIAG_CFG
        10. 7.5.2.10AFEDIAG_MASK
        11. 7.5.2.11COMPENSATION_CONTROL
        12. 7.5.2.12EEPROM_LOCK
        13. 7.5.2.13EEPROM_PAGE_ADDRESS
        14. 7.5.2.14EEPROM_CTRL
        15. 7.5.2.15EEPROM_CRC
        16. 7.5.2.16EEPROM_STATUS
        17. 7.5.2.17EEPROM_CRC_STATUS
        18. 7.5.2.18EEPROM_CRC_VALUE
  8. Application and Implementation
    1. 8.1Application Information
      1. 8.1.14-mA to 20-mA Output With Internal Sense Resistor
        1. 8.1.1.1Design Requirements
        2. 8.1.1.2Detailed Design Procedure
          1. 8.1.1.2.1Calibration Tips
            1. 8.1.1.2.1.1Programming the EEPROM for 4-mA to 20-mA Output
        3. 8.1.1.3Application Curve
      2. 8.1.20- to 10-V Absolute Output With Internal Drive
        1. 8.1.2.1Design Requirements
        2. 8.1.2.2Detailed Design Procedure
          1. 8.1.2.2.1Programmer Tips
            1. 8.1.2.2.1.1Resetting the Microprocessor and Enable Digital Interface
            2. 8.1.2.2.1.2Turning On the Accurate Reference Buffer (REFCAP Voltage)
            3. 8.1.2.2.1.3Turning On DAC and DAC GAIN
      3. 8.1.30- to 5-V Ratiometric Output With Internal Drive
        1. 8.1.3.1Design Requirements
        2. 8.1.3.2Detailed Design Procedure
          1. 8.1.3.2.1Programmer Tips
            1. 8.1.3.2.1.1Resetting the Microprocessor and Enable Digital Interface
            2. 8.1.3.2.1.2Turning On the Accurate Reference Buffer (REFCAP Voltage)
            3. 8.1.3.2.1.3Turning On DAC and DAC GAIN
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Trademarks
    2. 11.2Electrostatic Discharge Caution
    3. 11.3Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

1 Features

  • Analog Features
    • Analog Front-End for Resistive Bridge Sensors
    • Accommodates Sensor Sensitivities From 1 mV/V to 135 mV/V
    • On-Chip Temperature Sensor
    • Programmable Gain
    • 16-Bit Sigma-Delta Analog-to-Digital Converter for Signal Channel
    • 16-Bit Sigma-Delta Analog-to-Digital Converter for Temperature Channel
    • 14-Bit Output DAC
  • Digital Features
    • <0.1% FSO Accuracy Across Temperature
    • System Response Time <220 µs
    • Third-Order Offset, Gain, and Nonlinearity Temperature Compensation
    • Diagnostic Functions
    • Integrated EEPROM for Device Operation, Calibration Data and User Data
  • Peripheral Features
    • One-Wire Interface Enables Communication Through the Power Supply Pin Without Using Additional Lines
    • 4-mA to 20-mA Current Loop Interface
    • Ratiometric and Absolute Voltage Output
    • Power Management Control
    • Analog Low-Voltage Detect
  • General Features
    • Industrial Temperature Range: –40°C to 150°C
    • Power Supply:
      • On-Chip Power Management Accepts Wide Power-Supply Voltage From 3.3 V to 30 V
      • Integrated Reverse-Protection Circuit

2 Applications

  • Pressure-Sensor Transmitter and Transducer
  • Liquid-Level Meter, Flow Meter
  • Resistive Field Transmitter

3 Description

The PGA300 device provides an interface for piezoresistive and strain-gauge pressure-sense elements. The device is a full system-on-chip (SoC) solution that incorporates programmable analog front end (AFE), ADC, and digital signal processing that enable direct connection to the sense element. Further, the PGA300 device includes integrated voltage regulators and an oscillator, thus minimizing the number of external components. The device achieves high accuracy by employing third-order temperature and nonlinearity compensation. External communication is achieved by using a one-wire serial interface (OWI) through the power-supply pin in order to simplify the system calibration process. An Integrated DAC supports absolute-voltage, ratiometric-voltage, and 4-mA to 20-mA current-loop outputs.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
PGA300VQFN (36)6.00 mm × 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

PGA300 Simplified Block Diagram

PGA300 fbd_pga300_SLDS204.gif