SLDS186A March 2012  – July 2016 PGA400-Q1

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
    1. 3.1Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Overvoltage Protection Characteristics
    6. 6.6 Regulator Characteristics
    7. 6.7 Internal Oscillator and External Crystal Interface Characteristics
    8. 6.8 Sensor Supply Characteristics
    9. 6.9 Temperature Sensor Characteristics
    10. 6.10Stage 1 Gain Characteristics of the Analog Front End for Resistive Bridge Sensors
    11. 6.11Stage 2 Gain Characteristics
    12. 6.12Offset and Offset TC Compensation Characteristics
    13. 6.13ADC Characteristics
    14. 6.14OWI Characteristics
    15. 6.15SPI Characteristics
    16. 6.16I2C Interface Characteristics
    17. 6.17Non-Volatile Memory Characteristics
    18. 6.18GPIO Characteristics
    19. 6.19DAC1 and DAC2 Output Characteristics
    20. 6.20Input Capture and Output Compare Port Characteristics
    21. 6.21Diagnostic Characteristics
    22. 6.22SPI Timing Requirements
    23. 6.23I2C Interface Timing Requirements
    24. 6.24Typical Characteristics
  7. Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1 Overvoltage and Reverse Voltage Protection Block
      2. 7.2.2 Linear Regulators and Bandgap + Current Blocks
      3. 7.2.3 Internal OSC/XTAL I/F Block
      4. 7.2.4 Sensor Voltage Supply Block
        1. 7.2.4.1VBRG Supply for Resistive Bridge Sensors
        2. 7.2.4.2ICAP Supply for Capacitive Sensors
      5. 7.2.5 Internal Temperature Block and External Temperature Sensing
        1. 7.2.5.1Internal Temperature Sensor
        2. 7.2.5.2External Temperature Sensor
      6. 7.2.6 Using the Analog Front End
      7. 7.2.7 Stage 1 Gain Block
      8. 7.2.8 Self Oscillating Demodulator Block
        1. 7.2.8.1Configuring the Capacitive Sensor Interface for a Particular Sensor
      9. 7.2.9 Sign Bit Block
      10. 7.2.10Offset and Offset TC Compensation Blocks
      11. 7.2.11Stage 2 Gain Block
      12. 7.2.12ADC Buffer Blocks
        1. 7.2.12.1Analog to Digital Converter Buffer 1
        2. 7.2.12.2Analog to Digital Converter Buffer 2
      13. 7.2.13Sigma Delta Modulator Blocks
        1. 7.2.13.1Sigma Delta Modulator for AD Converter 1
        2. 7.2.13.2Sigma Delta Modulator for AD Converter 2
      14. 7.2.14Decimation Filter Blocks
        1. 7.2.14.1ADC1 Decimation Filter Blocks
        2. 7.2.14.2Decimation Filters for AD Converter 2
        3. 7.2.14.3Accessing the ADC Values for the 8051
      15. 7.2.158051 Warp Microprocessor Block
      16. 7.2.16Digital Interface
      17. 7.2.17One-Wire Interface (OWI)
        1. 7.2.17.1Overview of OWI
          1. 7.2.17.1.1OWI Protocol
            1. 7.2.17.1.1.1Standard Field Structure
            2. 7.2.17.1.1.2Frame Structure
            3. 7.2.17.1.1.3Sync Field
            4. 7.2.17.1.1.4Command Field
            5. 7.2.17.1.1.5Data Field(s)
          2. 7.2.17.1.2OWI Operations
            1. 7.2.17.1.2.1Write Operation
            2. 7.2.17.1.2.2Read Operation
          3. 7.2.17.1.3OWI Commands
            1. 7.2.17.1.3.1OWI Write Command
            2. 7.2.17.1.3.2OWI Read Initialization Command
            3. 7.2.17.1.3.3OWI Read Response Command
            4. 7.2.17.1.3.4OWI Burst Write Command (EEPROM Cache Access)
            5. 7.2.17.1.3.5OWI Burst Read Command (EEPROM Cache Access)
          4. 7.2.17.1.4OWI Communication Error Status
        2. 7.2.17.2Activating and Deactivating the OWI
          1. 7.2.17.2.1Activating OWI Communication
          2. 7.2.17.2.2Deactivating OWI Communication
      18. 7.2.18SPI
        1. 7.2.18.1Overview of SPI
        2. 7.2.18.2SPI Interface Protocol
          1. 7.2.18.2.1SPI Master to PGA400 Commands
          2. 7.2.18.2.2PGA400-Q1 to SPI Master Response
          3. 7.2.18.2.3SPI Command Examples
        3. 7.2.18.3Clocking Details
      19. 7.2.19I2C Interface
        1. 7.2.19.1Overview of I2C Interface
        2. 7.2.19.2I2C Interface Protocol
        3. 7.2.19.3Activating the I2C Interface
        4. 7.2.19.4Clocking Details of I2C Interface
    3. 7.3 Programming and Memory
      1. 7.3.1OTP Memory
      2. 7.3.2EEPROM Memory
        1. 7.3.2.1EEPROM Memory Organization
          1. 7.3.2.1.1EEPROM Cache
          2. 7.3.2.1.2Bank 0
          3. 7.3.2.1.3Banks 1-4
          4. 7.3.2.1.4Bank 5
          5. 7.3.2.1.5EEPROM Control and Status Registers (ESFR and Test)
            1. 7.3.2.1.5.1Digital Interface EEPROM Control Register
            2. 7.3.2.1.5.28051W EEPROM Program Register (Used with Bank 0 only)
            3. 7.3.2.1.5.3Microprocessor Reset/Interface Control Register
            4. 7.3.2.1.5.4EEPROM Status Register
          6. 7.3.2.1.6Accessing data from EEPROM Banks
            1. 7.3.2.1.6.1EEPROM Cache Load Process
          7. 7.3.2.1.7Programming EEPROM Banks
            1. 7.3.2.1.7.1Programming Bank 0
          8. 7.3.2.1.8Programming Banks 1-5
          9. 7.3.2.1.9CRC Calculation, Validation, and Storage for Banks 1-5
      3. 7.3.3RAM Memory
      4. 7.3.4SFR/ESFR Memory
      5. 7.3.5Test Register Memory
    4. 7.4 General Purpose Input Output (GPIO) Pins
      1. 7.4.1Setting the GPIO Functions
      2. 7.4.2GPIO Buffers
    5. 7.5 8051W UART
    6. 7.6 DAC Output
    7. 7.7 Input Capture and Output Compare
      1. 7.7.1Free Running Timer
      2. 7.7.2Input Capture
      3. 7.7.3Output Compare
    8. 7.8 Diagnostics
      1. 7.8.1 Power Supply Diagnostics
      2. 7.8.2 Resistive Bridge Sensor Connectivity Diagnostics
      3. 7.8.3 AFE Diagnostics
      4. 7.8.4 Internal Capacitors for Capacitive Sensor Diagnostics
      5. 7.8.5 DAC Diagnostics
      6. 7.8.6 Harness Open Wire Diagnostics
      7. 7.8.7 EEPROM CRC and Trim Error
      8. 7.8.8 RAM MBIST
      9. 7.8.9 Main Oscillator Watchdog
      10. 7.8.10Software Watchdog
    9. 7.9 Low-Power Mode
    10. 7.10Register Maps
      1. 7.10.18051W Memory Map
      2. 7.10.2SFR
        1. 7.10.2.1 I/O PORTS(P0,P1,P2,P3)
        2. 7.10.2.2 Stack Pointer (SP)
        3. 7.10.2.3 Data Pointer (DPTR)
        4. 7.10.2.4 Power Control Register (PCON)
        5. 7.10.2.5 Timer/Counter Control (TCON)
        6. 7.10.2.6 Timer/Counter Mode (TMOD)
        7. 7.10.2.7 Timer/Counter Data (TL0 TL1 TH0 TH1)
        8. 7.10.2.8 UART Control (SCON)
        9. 7.10.2.9 UART Data (SBUF)
        10. 7.10.2.10Interrupt Enable Register 0 (IE)
        11. 7.10.2.11Interrupt Enable Register 1 (IE1)
        12. 7.10.2.12Interrupt Priority Register 0 (IP)
        13. 7.10.2.13Interrupt Priority Register 1 (IP1)
        14. 7.10.2.14Program Status Word (PSW)
        15. 7.10.2.15Accumulator (ACC)
        16. 7.10.2.16Register (B)
      3. 7.10.3ESFR
        1. 7.10.3.1 PSMON Diagnostics Status (PSMON1, PSMON2)
        2. 7.10.3.2 AFE Diagnostics Status (AFEDIAG)
        3. 7.10.3.3 CPU Watchdog (CLKDIAG)
        4. 7.10.3.4 Sensor 1 Gain Register (SEN1GAIN)
        5. 7.10.3.5 Sensor 2 Gain Register (SEN2GAIN)
        6. 7.10.3.6 Sensor 1 Offset Register (SEN1OFF1, SEN1OFF2)
        7. 7.10.3.7 Sensor 2 Offset Register(SEN2OFF1, SEN2OFF2)
        8. 7.10.3.8 Capacitive Sensor Settings Register (CAPSEN)
        9. 7.10.3.9 Sensor Control (SENCTRL)
        10. 7.10.3.10GPIO Strong Output Drive Mode (GPIO_STRG)
        11. 7.10.3.11CTOV clock Count Register (CTOV_CLK_CNT)
        12. 7.10.3.12ADC Decimator Output (ADCMSB, ADCLSB)
        13. 7.10.3.13Load ADC Decimator Shadow Register (LD_DEC)
        14. 7.10.3.14DAC 1 Register (DAC1MSB, DAC1LSB)
        15. 7.10.3.15DAC 2 Register (DAC2MSB, DAC2LSB)
        16. 7.10.3.16Decimator and Low Power Control Register (DECCTRL)
        17. 7.10.3.17Input Capture/Output Compare Control Register (IC_OC_CTRL)
        18. 7.10.3.18Input Capture 1 Register (IC1MSB, IC1LSB)
        19. 7.10.3.19Input Capture 2 Register (IC2MSB, IC2LSB)
        20. 7.10.3.20Output Compare 1 Register (OC1MSB, OC1LSB)
        21. 7.10.3.21Input Capture/Output Compare GPIO Register (IC_OC_GPIO)
        22. 7.10.3.22Output Compare 2 Register (OC2MSB, OC2LSB)
        23. 7.10.3.23Free Running Timer Shadow Register (FRTMSB, FRTLSB)
        24. 7.10.3.24Communication Data Buffer (COMBUF)
        25. 7.10.3.25Digital Interface Control Register (DI_CTRL)
        26. 7.10.3.26Enable Control Register (EN_CTRL)
        27. 7.10.3.27Enable Control Register (EN_CTRL2)
        28. 7.10.3.28RAM MBIST Status Register (RAM_MBIST_ST)
        29. 7.10.3.29EEPROM Status Register (EE_STATUS)
        30. 7.10.3.30EEPROM Control Register (EE_CTRL)
      4. 7.10.4Test Registers
        1. 7.10.4.1 Test MUX Activation Register (TESTMUX_ACT)
        2. 7.10.4.2 Communication Data Buffer (COMBUF_T)
        3. 7.10.4.3 Communication Data Buffer Ready (COMBUF_R)
        4. 7.10.4.4 Analog Test MUX Out Register (AMUX_O)
        5. 7.10.4.5  Digital Test MUX Out Register (DMUX_O)
        6. 7.10.4.6 Analog Test MUX In Register (AMUX_I)
        7. 7.10.4.7 Digital Test MUX In Register (DMUX_I)
        8. 7.10.4.8 EEPROM Access Control Register (EEPROM_A)
        9. 7.10.4.9 Micro/Interface Control Register (MICRO_IF_SEL_T)
        10. 7.10.4.10OWI Error Status 1 (OWI_ERR_1)
        11. 7.10.4.11OWI Error Status 2 (OWI_ERR_2)
      5. 7.10.58051W Interrupts
        1. 7.10.5.1Standard Interrupts
        2. 7.10.5.2Extended Interrupts
          1. 7.10.5.2.1Interrupt Flag Clear
          2. 7.10.5.2.2Priority Levels / Interrupt Vectors
          3. 7.10.5.2.3Interrupt Latency
      6. 7.10.68051 Instructions
        1. 7.10.6.1Addressing Modes
          1. 7.10.6.1.1Direct Addressing
          2. 7.10.6.1.2Indirect Addressing
          3. 7.10.6.1.3Register Addressing
          4. 7.10.6.1.4Register Specific Addressing
          5. 7.10.6.1.5Immediate Data
          6. 7.10.6.1.6Indexed Addressing
        2. 7.10.6.2Arithmetic Instructions
        3. 7.10.6.3Logical Instructions
        4. 7.10.6.4Data Transfers
          1. 7.10.6.4.1Internal Data Memory
          2. 7.10.6.4.2External Data Memory
        5. 7.10.6.5Jump Instructions
          1. 7.10.6.5.1Unconditional Jumps
          2. 7.10.6.5.2Subroutine Calls and Returns
          3. 7.10.6.5.3Conditional Jumps
          4. 7.10.6.5.4Boolean Instructions
        6. 7.10.6.6Flags
        7. 7.10.6.7 Instruction Table
  8. Application and Implementation
    1. 8.1Typical Application
      1. 8.1.1Resistive Bridge Interface
        1. 8.1.1.1Capacitive Sensor Interface
  9. Device and Documentation Support
    1. 9.1Documentation Support
      1. 9.1.1Related Documentation
    2. 9.2Receiving Notification of Documentation Updates
    3. 9.3Community Resources
    4. 9.4Trademarks
    5. 9.5Electrostatic Discharge Caution
    6. 9.6Glossary
  10. 10Mechanical, Packaging, and Orderable Information

1 Features

  • Analog Features
    • Analog Front-End for Resistive Bridge Sensors
    • Self-Oscillating Demodulator for Capacitive Sensors
    • On-Chip Temperature Sensor
    • Programmable Gain
    • 16-Bit, 1-MHz Sigma-Delta Analog-to-Digital Converter for Signal Channel
    • 10-Bit Sigma-Delta Analog-to-Digital Converter for Temperature Channel
    • Two 12-Bit Digital-to-Analog Outputs
  • Digital Features
    • Microcontroller Core
      • 10-MHz 8051 WARP Core
        • 2 Clocks Per Instruction Cycle
      • On-Chip Oscillator
    • Memory
      • 8KB of OTP Memory
      • 89 Bytes of EEPROM
      • 256 Bytes Data SRAM
  • Peripheral Features
    • Serial Peripheral Interface (SPI)
    • Inter-Integrated Circuit (I2C)
    • One-Wire Interface (OWI)
    • Two Input Capture Ports
    • Two Output Compare Ports
    • Software Watchdog Timer
    • Oscillator Watchdog
    • Power Management Control
    • Analog Low-Voltage Detect
  • General Features
    • AEC-Q100 Qualified With the Following Results:
      • Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature
      • Device HBM ESD Classification Level 2
      • Device HBM ESD Classification Level C3B
    • Power Supply: 4.5-V to 5.5-V Operational, –5.5-V to 16-V Absolute Maximum

2 Applications

  • Pressure Sensor-Signal Conditioning
  • Level Sensor-Signal Conditioning
  • Humidity Sensor-Signal Conditioning

3 Description

The PGA400-Q1 device is an interface device for piezoresistive, strain gauge, and capacitive-sense elements. The device incorporates the analog front end (AFE) that directly connects to the sense element and has voltage regulators and an oscillator. The device also includes a sigma-delta analog-to-digital converter (ADC), 8051 WARP core microprocessor, and OTP memory. Sensor compensation algorithms can be implemented in software. The PGA400-Q1 device also includes two digital-to-analog converter (DAC) outputs.

Table 1. Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
PGA400QRHHRQ1VQFN (36)6.00 mm × 6.00 mm
PGA400QYZRQ1WCSP (36)3.65 mm × 3.65 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

3.1 Simplified Schematic

PGA400-Q1 FBD2.png

4 Revision History

Changes from * Revision (March 2012) to A Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Application and Implementation section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Added RHH packageGo
  • Added Typical Characteristics sectionGo
  • Added information for RHH package to Detailed Description sectionGo
  • Added Register Maps sectionGo