SLASE76E November 2015  – August 2017 PGA411-Q1

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Exciter Output, Amplifier, and Power Supply Characteristics
    6. 6.6 Analog Front-End Characteristics
    7. 6.7 Digital Tracking Loop Characteristics
    8. 6.8 Diagnostics Monitor Characteristics
    9. 6.9 VDD Regulator Characteristics
    10. 6.10Digital I/O Characteristics
    11. 6.11Oscillator Characteristics
    12. 6.12Output Data Interface Characteristics
    13. 6.13SPI Interface Timing Requirements
    14. 6.14Timing Diagrams
    15. 6.15Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1 Exciter Amplifier Power Supply
      2. 7.3.2 Exciter Signal Generation
        1. 7.3.2.1Exciter Signal Generator
        2. 7.3.2.2Exciter Signal Preamplifier
        3. 7.3.2.3Exciter Output Power Amplifier
      3. 7.3.3 Analog Front-End
      4. 7.3.4 Tracking Loop
        1. 7.3.4.1Resolver-to-Digital Converter Theory of Operation
      5. 7.3.5 Automatic Offset Correction
      6. 7.3.6 Phase Offset Correction
        1. 7.3.6.1Manual Mode
        2. 7.3.6.2Auto Mode
        3. 7.3.6.3Diagnostics Monitor
          1. 7.3.6.3.1Analog Front-End (AFE) Diagnostics
            1. 7.3.6.3.1.1Input-Short to GND or Input-Short to Battery
            2. 7.3.6.3.1.2Input Mutual Short
            3. 7.3.6.3.1.3Input Open
            4. 7.3.6.3.1.4Tracking Loop Stability
            5. 7.3.6.3.1.5Signal Integrity Check
            6. 7.3.6.3.1.6Exciter Monitor
          2. 7.3.6.3.2Exciter Amplifier Diagnostics
            1. 7.3.6.3.2.1Single-Ended Overvoltage Output
            2. 7.3.6.3.2.2Differential Output Undervoltage and Overvoltage
            3. 7.3.6.3.2.3Exciter-Output Current Limit
          3. 7.3.6.3.3Thermal Protection
      7. 7.3.7 Clock Generation
        1. 7.3.7.1Loss-of-Clock Monitor
      8. 7.3.8 VDD Regulator
      9. 7.3.9 Digital Input and Output
      10. 7.3.10Output Data Interface
        1. 7.3.10.1Digital Parallel Output
        2. 7.3.10.2ORD Clock
        3. 7.3.10.3SPI Output
        4. 7.3.10.4Encoder-Emulated Output
        5. 7.3.10.5Analog Output
      11. 7.3.11Fault Reporting
    4. 7.4Device Functional Modes
      1. 7.4.1PGA411-Q1 Reset
      2. 7.4.2DIAGNOSTIC State
      3. 7.4.3NORMAL Operating State
      4. 7.4.4FAULT State
      5. 7.4.5EEPROM Memory
      6. 7.4.6Functional Diagnostics Modules
        1. 7.4.6.1Analog and Logical Built-In Self-Test
        2. 7.4.6.2Device Configuration CRC Protection
        3. 7.4.6.3Digital-Output Signal Monitor
        4. 7.4.6.4Output Data Parity
    5. 7.5Programming
      1. 7.5.1Address and Address-Echo Field
      2. 7.5.2Data Field
      3. 7.5.3Status Field
      4. 7.5.4SPI Frame CRC Field
      5. 7.5.5Device and EEPROM Unlock Procedure
    6. 7.6Register Maps
      1. 7.6.1SPI Register Map Layout Configuration
      2. 7.6.2REGMAP Registers
        1. 7.6.2.1 DEV_OVUV1 Register (Offset = 0h) [Factory Settings = 8B40h]
        2. 7.6.2.2 DEV_OVUV2 Register (Offset = 1h) [Factory Settings = 00EDh]
        3. 7.6.2.3 DEV_OVUV3 Register (Offset = 2h) [Factory Settings = FCFFh]
        4. 7.6.2.4 DEV_OVUV4 Register (Offset = 3h) [Factory Settings = 07E2h]
        5. 7.6.2.5 DEV_OVUV5 Register (Offset = 4h) [Factory Settings = 1C00h]
        6. 7.6.2.6 DEV_OVUV6 Register (Offset = 5h) [Factory Settings = 038Fh]
        7. 7.6.2.7 DEV_TLOOP_CFG Register (Offset = 6h) [Factory Settings = 0514h]
        8. 7.6.2.8 DEV_AFE_CFG Register (Offset = 7h) [Factory Settings = 0005h]
        9. 7.6.2.9 DEV_PHASE_CFG Register (Offset = 8h) [Factory Settings = 1400h]
        10. 7.6.2.10DEV_CONFIG1 Register (Offset = 9h) [Factory Settings = 0002h]
        11. 7.6.2.11DEV_CONTROL1 Register (Offset = Ah) [Factory Settings = 0000h]
        12. 7.6.2.12DEV_CONTROL2 Register (Offset = Bh) [Factory Settings = 0000h]
        13. 7.6.2.13DEV_CONTROL3 Register (Offset = Ch) [Factory Settings = 0000h]
        14. 7.6.2.14DEV_STAT1 Register (Offset = Dh) [Factory Settings = 0000h]
        15. 7.6.2.15DEV_STAT2 Register (Offset = Eh) [Factory Settings = 0000h]
        16. 7.6.2.16DEV_STAT3 Register (Offset = Fh) [Factory Settings = 0000h]
        17. 7.6.2.17DEV_STAT4 Register (Offset = 10h) [Factory Settings = 0000h]
        18. 7.6.2.18DEV_STAT5 Register (Offset = 11h) [Factory Settings = 0000h]
        19. 7.6.2.19DEV_STAT6 Register (Offset = 12h) [Factory Settings = 0000h]
        20. 7.6.2.20DEV_STAT7 Register (Offset = 13h) [Factory Settings = 0000h]
        21. 7.6.2.21DEV_CLCRC Register (Offset = 14h) [Factory Settings = 00CEh]
        22. 7.6.2.22DEV_CRC Register (Offset = 15h) [Factory Settings = 0000h]
        23. 7.6.2.23CRCCALC Register (Offset = 16h) [Factory Settings = 00FFh]
        24. 7.6.2.24DEV_EE_CTRL1 Register (Offset = 17h) [Factory Settings = 0000h]
        25. 7.6.2.25DEV_CRC_CTRL1 Register (Offset = 18h) [Factory Settings = 0000h]
        26. 7.6.2.26DEV_EE_CTRL4 Register (Offset = 19h) [Factory Settings = 0000h]
        27. 7.6.2.27DEV_UNLK_CTRL1 Register (Offset = 1Ah) [Factory Settings = 0000h]
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.1Resolver-to-Digital Converter
      2. 8.2.2Design Requirements
      3. 8.2.3Detailed Design Procedure
        1. 8.2.3.1Excitation Amplifier Design
        2. 8.2.3.2Boost Power Supply Component Calculations
        3. 8.2.3.3AFE External-Component Value Selection
          1. 8.2.3.3.1Exciter Signal-Path Output Calculation
      4. 8.2.4Application Curves
    3. 8.3System Examples
    4. 8.4Initialization Set Up
  9. Power Supply Recommendations
    1. 9.1Sequencing VIO and VCC
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Documentation Support
      1. 11.1.1Related Documentation
    2. 11.2Community Resource
    3. 11.3Trademarks
    4. 11.4Electrostatic Discharge Caution
    5. 11.5Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • Resolver-to-Digital Converter (RDC)
  • Exciter Preamplifier and Power Amplifier
  • Exciter-Boost Power Supply With Spread Spectrum
  • Analog Front-End
  • Automatic Offset Calibration
  • Type-II PI Controller Tracking Loop
  • Parallel, Encoder, or SPI Data Output
  • Analog Data Output
  • SafeTI™ Semiconductor Component
    • Designed for Functional Safety Applications
    • Developed According to the Requirements of ISO 26262
  • Automatic and Manual Phase Correction
  • Sensor-Input Fault Detection
  • Diagnostics Interrupt Output
  • Internal and External Oscillator
  • Analog and Logic Built-In Self-Test for Fault Detection
  • 64-Pin HTQFP PowerPAD™ IC Package

Applications

  • Motor Control
  • HEV/EV Motor Inverters
  • Electrical Power Steering
  • Integrated Start-Stop Generators
  • Servo Drives
  • AC Drives
  • Industrial Robots
  • CNC Machinery
  • Elevators and Lifts
  • Injection Molding Machinery

Description

The PGA411-Q1 device is a resolver-to-digital converter, with an integrated exciter-amplifier and boost-regulator power supply, that is capable of both exciting and reading the sine and cosine angle from a resolver sensor. The integration of the exciter amplifier and boost supply with protection in the PGA411-Q1 device enables cost reductions of the bill of materials (BOM) and space reductions on the printed-circuit board (PCB) because of the elimination of most external and passive components.

The PGA411-Q1 device also has an internal clock for generating a sine wave used for sensor excitation. The architecture of the analog front-end (AFE) allows the user to output 10 bits or 12 bits of resolution for the angle position and velocity. Because of high integration, the PGA411-Q1 device has diagnostics and protection on each internal block inside the device. The integrated diagnostics monitor can signal a fault condition through a dedicated pin which can be used as a MCU interrupt. These features allow flexibility in both resolver sensor choice and platform scalability. Additionally, the PGA411-Q1 was designed according to the requirements of ISO 26262 for functional safety applications.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
PGA411-Q1HTQFP (64)10.00 mm × 10.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified System Diagram

PGA411-Q1 alt_slase76.gif

Revision History

Changes from D Revision (April 2016) to E Revision

  • Updated data sheet text to the latest TI documentation and translation standardsGo
  • Changed the Electrical Characteristics test conditions from: VIN = 4.5 to: VIN = 4.75Go
  • Changed the VIZx parameter and unit informationGo
  • Removed the common-mode voltage output parameter from the Analog Front-End Characteristics tableGo
  • Updated Figure 2Go
  • Added content to the Exciter Signal Preamplifier section Go
  • Added content to the Exciter Output Power Amplifier section Go
  • Updated Figure 14 and added Table 1Go
  • Added new content to the Automatic Offset Correction section Go
  • Updated Figure 20 Go
  • Changed the undervoltage threshold of the 7-VRMS output-mode of operation from: 7 V to: 6 VGo
  • Removed content from the Exciter-Output Current Limit sectionGo
  • Added image and new content to the Digital Parallel Output sectionGo
  • Added new content to the ORD Clock section Go
  • Removed the ENFLOOPE option from the data sheetGo
  • Updated DEV_CONFIG1 data split info in Table 7Go
  • Updated register description for Bit 4-3 Go
  • Updated Table 41 and Table 42Go

Changes from C Revision (March 2016) to D Revision

  • Added the resistor to ground production statement in the Analog Output section and Pin Functions table and added the resistor to the PGA411-Q1 Typical Application Diagram image Go
  • Changed the factory setting from 003Fh (00111111b) to 00CEh (11001110b) for the DEV_CLCRC register in the User EEPROM Space SPI Mapping table and in the DEV_CLCRC Register sectionGo
  • Added a note to the Power Supply Recommendations section about the input supply when connected to VCC and QVCC pins Go

Changes from B Revision (December 2015) to C Revision

  • Changed the device status from Product Preview to Production Data Go