SLDS185D March 2012  – June 2016 PGA450-Q1

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: AEC Q100
    3. 6.3 ESD Ratings: IEC61000-4-2
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Electrical Characteristics — LIN 2.1 Slave and Buffered SCI
    8. 6.8 Electrical Characteristics — SPI Interface
    9. 6.9 Timing Requirements
    10. 6.10Timing Requirements — LIN 2.1 Slave and Buffered SCI
    11. 6.11Timing Requirements — SPI Interface
    12. 6.12Switching Characteristics
    13. 6.13Digital Datapath Filter Switching Characteristics
    14. 6.14Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1 Power Supply Block
      2. 7.3.2 VREG
      3. 7.3.3 Clock
        1. 7.3.3.1Clock Synchronizer Using the SYNC Field in the LIN Bus
      4. 7.3.4 Low-Side Drive FETs
      5. 7.3.5 Burst Generator
      6. 7.3.6 Low-Noise Amplifier
      7. 7.3.7 Analog-to-Digital Converter
      8. 7.3.8 Digital Data Path
        1. 7.3.8.1Bandpass Filter (BPF)
        2. 7.3.8.2Rectifier
        3. 7.3.8.3Peak Extractor
        4. 7.3.8.4Downsample
        5. 7.3.8.5Low-Pass Filter
        6. 7.3.8.6Datapath Output Format Control
        7. 7.3.8.7Datapath Activation and Blanking Timer
        8. 7.3.8.8Digital Datapath Output Mode
      9. 7.3.9 Transducer Saturation Time
      10. 7.3.10Temperature Sensor
      11. 7.3.11Free-Running Timer
      12. 7.3.12GPIOs
      13. 7.3.13 8051W UART
      14. 7.3.14 8051 WARP Core
      15. 7.3.15Memory
        1. 7.3.15.1FIFO Memory for Digital Datapath Output
        2. 7.3.15.2OTP Memory for Program
          1. 7.3.15.2.1OTP Security
          2. 7.3.15.2.2OTP Programming
        3. 7.3.15.3EEPROM Memory for Data
          1. 7.3.15.3.1EEPROM Memory Organization
            1. 7.3.15.3.1.1EEPROM Cache
            2. 7.3.15.3.1.2EEPROM Memory Cells
          2. 7.3.15.3.2Programming EEPROM Through the 8051W and SPI
          3. 7.3.15.3.3Reloading From EEPROM Cells Through the 8051W and SPI
      16. 7.3.16LIN 2.1 Slave and Buffered SCI
        1. 7.3.16.1Physical Layer
        2. 7.3.16.2LIN Slave Mode
          1. 7.3.16.2.1LIN Frame
          2. 7.3.16.2.2LIN Registers
          3. 7.3.16.2.3LIN Interrupts
          4. 7.3.16.2.4LIN Slave Configuration
            1. 7.3.16.2.4.1LIN Frame-Control Configuration
            2. 7.3.16.2.4.2LIN Timing-Control Configuration
          5. 7.3.16.2.5LIN Slave-Protocol State Machine
          6. 7.3.16.2.6LIN Slave Protocol Rx
          7. 7.3.16.2.7LIN Slave Protocol Tx
          8. 7.3.16.2.8LIN Slave Status
            1. 7.3.16.2.8.1LIN Slave Framing Error Status
            2. 7.3.16.2.8.2LIN Slave Timing Error Status
        3. 7.3.16.3SCI Buffered Mode
          1. 7.3.16.3.1SCI Buffered-Mode State Machine
          2. 7.3.16.3.2SCI Buffered-Mode Rx
          3. 7.3.16.3.3SCI Buffered-Mode Tx
        4. 7.3.16.4Connection of LIN Pin to 8051W
    4. 7.4Device Functional Modes
      1. 7.4.1Active Mode
      2. 7.4.2Quiet Mode
      3. 7.4.3RESET
    5. 7.5Programming
      1. 7.5.1 SPI Interface
        1. 7.5.1.1SPI Interface Protocol
        2. 7.5.1.2Transfer Width
        3. 7.5.1.3CheckByte
        4. 7.5.1.4Examples
      2. 7.5.2Diagnostics
        1. 7.5.2.1Power-Block Monitors
        2. 7.5.2.2Low-Side Diagnostics
        3. 7.5.2.3Main Oscillator Watchdog
        4. 7.5.2.4Software Watchdog
        5. 7.5.2.5Internal ASIC TRIM Validity
        6. 7.5.2.6FIFO RAM and External SRAM MBIST
        7. 7.5.2.7Thermal Shutdown
      3. 7.5.38051W Interrupts
        1. 7.5.3.1Interrupt Flag Clear
        2. 7.5.3.2Priority Levels and Interrupt Vectors
        3. 7.5.3.3Interrupt Latency
      4. 7.5.4Instructions
        1. 7.5.4.1Addressing Modes
          1. 7.5.4.1.1Direct Addressing
          2. 7.5.4.1.2Indirect Addressing
          3. 7.5.4.1.3Register Addressing
          4. 7.5.4.1.4Register Specific Addressing
          5. 7.5.4.1.5Immediate Data
          6. 7.5.4.1.6Indexed Addressing
        2. 7.5.4.2Arithmetic Instructions
        3. 7.5.4.3Logical Instructions
        4. 7.5.4.4Data Transfers
          1. 7.5.4.4.1Internal Data Memory
          2. 7.5.4.4.2External Data Memory
        5. 7.5.4.5Jump Instructions
          1. 7.5.4.5.1Unconditional Jumps
          2. 7.5.4.5.2Subroutine Calls and Returns
          3. 7.5.4.5.3Conditional Jumps
        6. 7.5.4.6Boolean Instructions
        7. 7.5.4.7Flags
        8. 7.5.4.8Instruction Table
      5. 7.5.58051W Port Usage
    6. 7.6Register Maps
      1. 7.6.1SFR Registers
        1. 7.6.1.1 I/O Ports (P0, P1, P2, P3) Registers
          1. 7.6.1.1.1I/O Port 3 Register (offset = 0xB0) [reset = 0xFF]
          2. 7.6.1.1.2I/O Port 2 Register (offset = 0xA0) [reset = 0xFF]
          3. 7.6.1.1.3I/O Port 1 Register (offset = 0x90) [reset = 0xFF]
          4. 7.6.1.1.4I/O Port 0 (P0) (offset = 0x80) [reset = 0xFF]
        2. 7.6.1.2 Stack Pointer Register (offset = 0x81) [reset = 0]
        3. 7.6.1.3 Data Pointer Registers
          1. 7.6.1.3.1Data Pointer Register (offset = 0x82) [reset = 0]
          2. 7.6.1.3.2Data Pointer Register (offset = 0x83) [reset = 0]
        4. 7.6.1.4 Power Control Register (offset = 0x87) [reset = 0]
        5. 7.6.1.5 Timer and Counter Control Register (offset = 0x88) [reset = 0]
        6. 7.6.1.6 Timer and Counter Mode Register (offset = 0x89) [reset = 0]
        7. 7.6.1.7 Timer and Counter Data Registers (TL0, TL1, TH0, TH1)
          1. 7.6.1.7.1TL0 Register (offset = 0x8A) [reset = 0]
          2. 7.6.1.7.2TL1 Register (offset = 0x8B) [reset = 0]
          3. 7.6.1.7.3TH0 Register (offset = 0x8C) [reset = 0]
          4. 7.6.1.7.4TH1 Register (offset = 0x8D) [reset = 0]
        8. 7.6.1.8 UART Control Register (offset = 0x98) [reset = 0]
        9. 7.6.1.9 UART Data Register (offset = 0x99) [reset = 0]
        10. 7.6.1.10Interrupt Enable Register 0 (offset = 0xA8) [reset = 0]
        11. 7.6.1.11Interrupt Enable Register 1 (offset = 0xE8) [reset = 0]
        12. 7.6.1.12Interrupt Priority Register 0 (offset = 0xB8) [reset = 0]
        13. 7.6.1.13Interrupt Priority Register 1 (offset = 0xF8) [reset = 0]
        14. 7.6.1.14Program Status Word Register (offset = 0xD0) [reset = 0]
        15. 7.6.1.15Accumulator Register (offset = 0xE0) [reset = 0]
        16. 7.6.1.16B Register (offset = 0xF0) [reset = 0]
      2. 7.6.2ESFR Registers
        1. 7.6.2.1 Bandpass Filter Coefficient B1 (BPF_B1) Register
          1. 7.6.2.1.1Bandpass Filter B1 MSB Register (offset = 0x92) [reset = 0]
          2. 7.6.2.1.2Bandpass Filter B1 LSB Register (offset = 0x93) [reset = 0]
        2. 7.6.2.2 Bandpass Filter Coefficient A2 (BPF_A2) Registers
          1. 7.6.2.2.1Bandpass Filter Coefficient A2 MSB Register (offset = 0x94) [reset = 0]
          2. 7.6.2.2.2Bandpass Filter Coefficient A2 LSB Register (offset = 0x95) [reset = 0]
        3. 7.6.2.3 Band-Pass Filter Coefficient A3 (BPF_A3) Register
          1. 7.6.2.3.1Band-Pass Filter Coefficient A3 MSB Register (offset = 0x96) [reset = 0]
          2. 7.6.2.3.2Band-Pass Filter Coefficient A3 LSB Register (offset = 0x97) [reset = 0]
        4. 7.6.2.4 Low-Pass Filter Coefficient B1 (LPF_B1) Registers
          1. 7.6.2.4.1Low-Pass Filter Coefficient B1 MSB Register (offset = 0xA1) [reset = 0]
          2. 7.6.2.4.2Low-Pass Filter Coefficient B1 LSB Register (offset = 0xA2) [reset = 0]
        5. 7.6.2.5 Low-Pass Filter Coefficient A2 (LPF_A2) Registers
          1. 7.6.2.5.1Low-Pass Filter Coefficient A2 MSB Register (offset = 0xA3) [reset = 0]
          2. 7.6.2.5.2Low-Pass Filter Coefficient A2 LSB Register (offset = 0xA4) [reset = 0]
        6. 7.6.2.6 Downsample Register (offset = 0xA5) [reset = 0]
        7. 7.6.2.7 BURST ON A Duration (ON_A) Registers
          1. 7.6.2.7.1BURST ON A Duration MSB Register (offset = 0xA6) [reset = 0]
          2. 7.6.2.7.2BURST ON A Duration LSB Register (offset = 0xA7) [reset = 0]
        8. 7.6.2.8 BURST OFFA Duration (OFF_A) Register
          1. 7.6.2.8.1BURST OFFA Duration MSB Register (offset = 0xA9) [reset = 0]
          2. 7.6.2.8.2BURST OFFA Duration LSB Register (offset = 0xAA) [reset = 0]
        9. 7.6.2.9 BURST ON B Duration (ON_B) Registers
          1. 7.6.2.9.1BURST ON B Duration MSB Register (offset = 0xAB) [reset = 0]
          2. 7.6.2.9.2BURST ON B Duration LSB Register (offset = 0xAC) [reset = 0]
        10. 7.6.2.10BURST OFF B Duration (OFF_B) Register
          1. 7.6.2.10.1BURST OFF B Duration MSB Register (offset = 0xAD) [reset = 0]
          2. 7.6.2.10.2BURST OFF B Duration LSB Register (offset = 0xAE) [reset = 0]
        11. 7.6.2.11Pulse Count A Register (offset = 0xAF) [reset = 0]
        12. 7.6.2.12Pulse Count B Register (offset = 0xB1) [reset = 0]
        13. 7.6.2.13Deadtime Register (offset = 0xB2) [reset = 0]
        14. 7.6.2.14Burst Mode Register (offset = 0xB3) [reset = 0]
        15. 7.6.2.15Temperature Sensor Register (offset = 0xB4) [reset = 0]
        16. 7.6.2.16Saturation Deglitch Time Register (offset = 0xB5) [reset = 0]
        17. 7.6.2.17Saturation Time Capture Register (offset = 0xB6) [reset = 0]
        18. 7.6.2.18Control 1 Register (offset = 0xB7) [reset = 0]
        19. 7.6.2.19Blanking Timer Register (offset = 0xB9) [reset = 0]
        20. 7.6.2.20Free Running Timer (FRT) Registers
          1. 7.6.2.20.1Free Running Timer MSB Registers (offset = 0xBA) [reset = 0]
          2. 7.6.2.20.2Free Running Timer LSB Registers (offset = 0xBB) [reset = 0]
        21. 7.6.2.21GPIO Control Register (offset = 0xBC) [reset = 0]
        22. 7.6.2.22Clock Select Register (offset = 0xBD) [reset = 0]
        23. 7.6.2.23Watchdog Enable Register (offset = 0xBE) [reset = 0]
        24. 7.6.2.24LIN/SCI Select Register (offset = 0xBF) [reset = 0]
        25. 7.6.2.25EEPROM Control Register (offset = 0xC0) [reset = 0]
        26. 7.6.2.26Status 1 (STATUS1) Register (offset = 0xC1) [reset = 0]
        27. 7.6.2.27Status 2 Register (offset = 0xC2) [reset = 0]
        28. 7.6.2.28Power Mode Register (offset = 0xC3) [reset = 0]
        29. 7.6.2.29Datapath and SCI Control Register (offset = 0xC4) [reset = 0]
        30. 7.6.2.30FIFO Control Register (offset = 0xC5) [reset = ]
        31. 7.6.2.31Enable Control Register (offset = 0xC8) [reset = 0]
        32. 7.6.2.32LIN/SCI Rx Data (RX_DATAx) Register (offset = 0xC9 to 0xD1) [reset = 0]
        33. 7.6.2.33LIN PID Register (offset = 0xD2) [reset = 0]
        34. 7.6.2.34LIN/SCI Tx Data Registers (offset = 0xD3 to 0xDA) [reset = 0]
        35. 7.6.2.35LIN/SCI Data Count Register (offset = 0xDB) [reset = 0]
        36. 7.6.2.36LIN Configuration Register (offset = 0xDC) [reset = 0x40]
        37. 7.6.2.37LIN Control Register (offset = 0xDD) [reset = 0]
        38. 7.6.2.38LIN STATUS Register (offset = 0xDE) [reset = 0]
        39. 7.6.2.39FIFO Pointer (FIFO_POINTER) Registers
          1. 7.6.2.39.1FIFO Pointer MSB Register (offset = 0xDF) [reset = 0]
          2. 7.6.2.39.2FIFO Pointer LSB Register (offset = 0xE1) [reset = 0]
        40. 7.6.2.40VREG Select Register (offset = 0xE2) [reset = 0]
        41. 7.6.2.41Sync Count (SYNC_COUNT) Registers
          1. 7.6.2.41.1Sync Count MSB Register (offset = 0xE3) [reset = 0]
          2. 7.6.2.41.2Sync Count LSB Register (offset = 0xE4) [reset = 0]
        42. 7.6.2.42TEMP/DAC Control Register (offset = 0xE5) [reset = 0]
        43. 7.6.2.43Oscillator Sync Control Register (offset = 0xE6) [reset = 0]
      3. 7.6.3TEST Registers
        1. 7.6.3.1ANALOG Test MUX Register (offset = 0xE9) [reset = 0]
        2. 7.6.3.2DIGITAL Test MUX Register (offset = 0xEA) [reset = 0]
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.1Design Parameters
      2. 8.2.2Detailed Design Procedure
        1. 8.2.2.1Hardware
        2. 8.2.2.2Firmware
          1. 8.2.2.2.1Band-pass Filter Coefficients
          2. 8.2.2.2.2Downsample Rate
          3. 8.2.2.2.3Low-Pass Filter Coefficients
          4. 8.2.2.2.4Pulse Count
          5. 8.2.2.2.5Blanking Timer
          6. 8.2.2.2.6FIFO Mode
        3. 8.2.2.3OUT_A and OUT_B On and Off Times
      3. 8.2.3Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Documentation Support
      1. 11.1.1Related Documentation
    2. 11.2Community Resource
    3. 11.3Trademarks
    4. 11.4Electrostatic Discharge Caution
    5. 11.5Glossary
  12. 12Mechanical, Packaging, and Orderable Information

1 Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range
    Measurements up to 7 Meters through Air
  • Dual NMOS Low-Side Drivers
  • Configurable Burst Generator
  • Low-Noise Amplifier
  • 12-Bit SAR ADC
  • Configurable Digital Bandpass Filter
  • Digital Signal Envelope Detect
  • On-Chip 8-Bit Microprocessor
  • LIN 2.1 Physical Interface and Protocol
  • Watchdog Timer
  • Four-Wire SPI for Testability and Programming
  • 8K Bytes of OTP
  • 768 Bytes of FIFO RAM
  • 256 Bytes of Scratchpad RAM
  • 8K Bytes of Development RAM
  • 32 Bytes of EEPROM for Application

2 Applications

  • Automotive Ultrasonic Park Assist
  • Intrusion Detection
  • Proximity Sensing and Object Detection
  • Displacement Sensing
  • Large Tank Level Sensing
  • Landing Assistance for Drones
  • Collision-Avoidance for Drones, Robots and Unmanned Systems

3 Description

The PGA450-Q1 device is a fully integrated system-on-a-chip analog front-end for ultrasonic sensing in automotive park-assist, object-detection through air, level sensing in large tanks, and distance measurements for anti-collision and landing assist of unmanned systems (such as drones, cameras, and robots). This highly integrated device enables a small form-factor and cost-optimized solution compared to discrete ultrasonic-sensor solutions. The PGA450-Q1 device can measure distances ranging from less than 1 meter up to 7 meters, at a resolution of 1 cm depending on the transducer-transformer sensor pair used in the system.

The PGA450-Q1 device has an integrated 8051 8-bit microcontroller and OTP memory for program storage to process the echo signal and calculate the distance between the transducer and targeted object. Full programmability is available for optimization of specific end applications, and to accommodate a wide-range of closed-top or open-top transducers. Configurable variables include the number of transmit pulses, driving frequency, LNA gain, and comparison signal thresholds. External communication with the PGA450-Q1 device is capable through the LIN 2.1 protocol, SPI, or UART interfaces.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
PGA450-Q1TSSOP (28)9.70 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Diagram

PGA450-Q1 alt_lds185.gif

4 Revision History

Changes from C Revision (November 2015) to D Revision

  • Changed the bit numbers for the Byte #1 breakdown in the SPI Protocol Transfer Widths table Go
  • Added the byte #4 data for the external RAM read in the SPI Protocol Transfer Widths table Go
  • Changed the address of the OTP program code area from 0x1000 to 0x0000 in the PGA450 Memory Map figureGo
  • Changed the SAT_SEL0 value for 600 mV from 0 to 1 in the SAT_SELx Bit Configuration table Go

Changes from B Revision (June 2015) to C Revision

  • Added the measurements and AEC features to the Features sectionGo
  • Changed the list of applications in the Applications section Go
  • Changed the Description section Go
  • Moved the ESD rating for the IEC61000-4-2 specification into a separate ESD Ratings table Go
  • Changed the description of the push-pull drive mode configuration in the Burst Generator section Go
  • Changed the address and byte 3 data descriptions for the external RAM read and write in the SPI Protocol Transfer Widths table. Also changed the byte 4 description for the external RAM writeGo
  • Changed the hex code for INC @Ri in the Instructions tableGo
  • Added the timer usage for port 3, bit 5 in the 8051W I/O Port Usage in PGA450-Q1 tableGo

Changes from A Revision (April 2012) to B Revision

  • Changed Automotive Park Distance to Automotive Park Assist in the Applications and Description sectionsGo
  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go
  • Added the external crystal parameter to the Timing Requirements table Go
  • Changed active bit to ACTIVE_EN bit and added VREG_EN; updated Power-Up Waveforms figure in the Power Supply Block section.Go
  • Removed ; this field can be updated by the 8051W from the last paragraph in the Clock Synchronizer Using the SYNC Field in the LIN Bus section.Go
  • Updated the Burst Generator figureGo
  • Changed all instances of LS in to Low-side in Description column of Low-Side MOSFET Gate Drive Modes ITEM DESCRIPTION tableGo
  • Changed register names in the description column of the Low-Side MOSFET Gate Drive Modes ITEM DESCRIPTION table: ENABLE CONTROL to EN_CTRL, PULSE COUNT A to PULSE_CNTA, PULSE COUNT B to PULSE_CNTB, BURST_ONA to ON_A, BURST_OFFA to OFF_A, BURST_ONB to ON_B, BURST_OFFB to OFF_B. Removed Set by SFR from Description.Go
  • Changed For TI Use Only to Reserved.Go
  • Updated the Digital Data Path figureGo
  • Changed MODE bits to mode bits, changed FIFO CONTROL register to FIFO control register and added (FIFO_CTRL) to Datapath Output Format Control section.Go
  • Added (EN_CTRL) and changed ENABLE CONTROL register to enable control register in the Datapath Activation and Blanking Timer. Go
  • Updated the States of Digital Datapath figureGo
  • Changed ANALOG MUX ESFR to ANALOG_MUX ESFR, removed all caps for temperature sensor and digital datapath, changed TEMP_CTRL to TEMP_DAC_CTRL in the Digital Datapath Output Mode section. Go
  • Added (EN_CTRL), (SAT_DEGLITCH), and (SAT_TIME) register name definitions, changed uppercase register names to lower case, changed second bullet from: SATURATION THRESHOLD register to: Saturation threshold is set by the SAT_SEL1 and SAT_SEL0 bits in CONTROL_1 register in Transducer Saturation Time section.Go
  • Updated the Transducer Saturation-Time Measurement Block figureGo
  • Changed ENABLE CONTROL register to EN_CTRL, changed SATURATION DEGLITCH TIME register to SAT_DEGLITCH register, changed SATURATION TIME CAPTURE register to SAT_TIME register, changed sentence from: When this voltage goes below the programmed threshold in the SATURATION THRESHOLD register... to: When this voltage goes below the programmed saturation threshold...Go
  • Changed room temperature to 30°C; changed Temperature = 0.75 to Temperature = 1.75 in Temperature Sensor section.Go
  • Updated the Timing Diagram Showing the Measurement of Transducer Saturation Time figureGo
  • Changed FREE RUNNING TIMER to free-running timer, added (FRT) coin, changed register to ESFR, changed CAP_FR_TMR to CAP_FR_TIMER.Go
  • Added: which is stored in the FIFO_POINTER register to FIFO Memory for Digital Datapath Output section.Go
  • Deleted unless the entire OTP is erased by a UV-light EPROM eraser from the following sentence: After an address is programmed, it cannot be programmed again. in the OTP Programming section.Go
  • Removed: Use MOVX commands to place data in external memory addresses 0x0400 through 0x041F. Go
  • Updated the LIN Registers figureGo
  • Switched 1 and 0 under HOLD in LIN Frame-Control Configuration section.Go
  • Changed If there is a parity error... to: If there is no parity error... in LIN Slave-Protocol State Machine.Go
  • Updated the LIN Controller State Machine figureGo
  • Changed Rx to receive in LIN Slave Protocol Rx section.Go
  • Changed receive to transmit and TX to transmit in the LIN Slave Protocol Tx section.Go
  • Removed: of the PID field under STOP_BIT_VAL in the LIN Slave Framing Error Status section.Go
  • Changed CPU_WD_EN to SW_WD_EN.Go