SLDS185D
March 2012 – June 2016
PGA450-Q1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings: AEC Q100
6.3
ESD Ratings: IEC61000-4-2
6.4
Recommended Operating Conditions
6.5
Thermal Information
6.6
Electrical Characteristics
6.7
Electrical Characteristics — LIN 2.1 Slave and Buffered SCI
6.8
Electrical Characteristics — SPI Interface
6.9
Timing Requirements
6.10
Timing Requirements — LIN 2.1 Slave and Buffered SCI
6.11
Timing Requirements — SPI Interface
6.12
Switching Characteristics
6.13
Digital Datapath Filter Switching Characteristics
6.14
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Power Supply Block
7.3.2
VREG
7.3.3
Clock
7.3.3.1
Clock Synchronizer Using the SYNC Field in the LIN Bus
7.3.4
Low-Side Drive FETs
7.3.5
Burst Generator
7.3.6
Low-Noise Amplifier
7.3.7
Analog-to-Digital Converter
7.3.8
Digital Data Path
7.3.8.1
Bandpass Filter (BPF)
7.3.8.2
Rectifier
7.3.8.3
Peak Extractor
7.3.8.4
Downsample
7.3.8.5
Low-Pass Filter
7.3.8.6
Datapath Output Format Control
7.3.8.7
Datapath Activation and Blanking Timer
7.3.8.8
Digital Datapath Output Mode
7.3.9
Transducer Saturation Time
7.3.10
Temperature Sensor
7.3.11
Free-Running Timer
7.3.12
GPIOs
7.3.13
8051W UART
7.3.14
8051 WARP Core
7.3.15
Memory
7.3.15.1
FIFO Memory for Digital Datapath Output
7.3.15.2
OTP Memory for Program
7.3.15.2.1
OTP Security
7.3.15.2.2
OTP Programming
7.3.15.3
EEPROM Memory for Data
7.3.15.3.1
EEPROM Memory Organization
7.3.15.3.1.1
EEPROM Cache
7.3.15.3.1.2
EEPROM Memory Cells
7.3.15.3.2
Programming EEPROM Through the 8051W and SPI
7.3.15.3.3
Reloading From EEPROM Cells Through the 8051W and SPI
7.3.16
LIN 2.1 Slave and Buffered SCI
7.3.16.1
Physical Layer
7.3.16.2
LIN Slave Mode
7.3.16.2.1
LIN Frame
7.3.16.2.2
LIN Registers
7.3.16.2.3
LIN Interrupts
7.3.16.2.4
LIN Slave Configuration
7.3.16.2.4.1
LIN Frame-Control Configuration
7.3.16.2.4.2
LIN Timing-Control Configuration
7.3.16.2.5
LIN Slave-Protocol State Machine
7.3.16.2.6
LIN Slave Protocol Rx
7.3.16.2.7
LIN Slave Protocol Tx
7.3.16.2.8
LIN Slave Status
7.3.16.2.8.1
LIN Slave Framing Error Status
7.3.16.2.8.2
LIN Slave Timing Error Status
7.3.16.3
SCI Buffered Mode
7.3.16.3.1
SCI Buffered-Mode State Machine
7.3.16.3.2
SCI Buffered-Mode Rx
7.3.16.3.3
SCI Buffered-Mode Tx
7.3.16.4
Connection of LIN Pin to 8051W
7.4
Device Functional Modes
7.4.1
Active Mode
7.4.2
Quiet Mode
7.4.3
RESET
7.5
Programming
7.5.1
SPI Interface
7.5.1.1
SPI Interface Protocol
7.5.1.2
Transfer Width
7.5.1.3
CheckByte
7.5.1.4
Examples
7.5.2
Diagnostics
7.5.2.1
Power-Block Monitors
7.5.2.2
Low-Side Diagnostics
7.5.2.3
Main Oscillator Watchdog
7.5.2.4
Software Watchdog
7.5.2.5
Internal ASIC TRIM Validity
7.5.2.6
FIFO RAM and External SRAM MBIST
7.5.2.7
Thermal Shutdown
7.5.3
8051W Interrupts
7.5.3.1
Interrupt Flag Clear
7.5.3.2
Priority Levels and Interrupt Vectors
7.5.3.3
Interrupt Latency
7.5.4
Instructions
7.5.4.1
Addressing Modes
7.5.4.1.1
Direct Addressing
7.5.4.1.2
Indirect Addressing
7.5.4.1.3
Register Addressing
7.5.4.1.4
Register Specific Addressing
7.5.4.1.5
Immediate Data
7.5.4.1.6
Indexed Addressing
7.5.4.2
Arithmetic Instructions
7.5.4.3
Logical Instructions
7.5.4.4
Data Transfers
7.5.4.4.1
Internal Data Memory
7.5.4.4.2
External Data Memory
7.5.4.5
Jump Instructions
7.5.4.5.1
Unconditional Jumps
7.5.4.5.2
Subroutine Calls and Returns
7.5.4.5.3
Conditional Jumps
7.5.4.6
Boolean Instructions
7.5.4.7
Flags
7.5.4.8
Instruction Table
7.5.5
8051W Port Usage
7.6
Register Maps
7.6.1
SFR Registers
7.6.1.1
I/O Ports (P0, P1, P2, P3) Registers
7.6.1.1.1
I/O Port 3 Register (offset = 0xB0) [reset = 0xFF]
7.6.1.1.2
I/O Port 2 Register (offset = 0xA0) [reset = 0xFF]
7.6.1.1.3
I/O Port 1 Register (offset = 0x90) [reset = 0xFF]
7.6.1.1.4
I/O Port 0 (P0) (offset = 0x80) [reset = 0xFF]
7.6.1.2
Stack Pointer Register (offset = 0x81) [reset = 0]
7.6.1.3
Data Pointer Registers
7.6.1.3.1
Data Pointer Register (offset = 0x82) [reset = 0]
7.6.1.3.2
Data Pointer Register (offset = 0x83) [reset = 0]
7.6.1.4
Power Control Register (offset = 0x87) [reset = 0]
7.6.1.5
Timer and Counter Control Register (offset = 0x88) [reset = 0]
7.6.1.6
Timer and Counter Mode Register (offset = 0x89) [reset = 0]
7.6.1.7
Timer and Counter Data Registers (TL0, TL1, TH0, TH1)
7.6.1.7.1
TL0 Register (offset = 0x8A) [reset = 0]
7.6.1.7.2
TL1 Register (offset = 0x8B) [reset = 0]
7.6.1.7.3
TH0 Register (offset = 0x8C) [reset = 0]
7.6.1.7.4
TH1 Register (offset = 0x8D) [reset = 0]
7.6.1.8
UART Control Register (offset = 0x98) [reset = 0]
7.6.1.9
UART Data Register (offset = 0x99) [reset = 0]
7.6.1.10
Interrupt Enable Register 0 (offset = 0xA8) [reset = 0]
7.6.1.11
Interrupt Enable Register 1 (offset = 0xE8) [reset = 0]
7.6.1.12
Interrupt Priority Register 0 (offset = 0xB8) [reset = 0]
7.6.1.13
Interrupt Priority Register 1 (offset = 0xF8) [reset = 0]
7.6.1.14
Program Status Word Register (offset = 0xD0) [reset = 0]
7.6.1.15
Accumulator Register (offset = 0xE0) [reset = 0]
7.6.1.16
B Register (offset = 0xF0) [reset = 0]
7.6.2
ESFR Registers
7.6.2.1
Bandpass Filter Coefficient B1 (BPF_B1) Register
7.6.2.1.1
Bandpass Filter B1 MSB Register (offset = 0x92) [reset = 0]
7.6.2.1.2
Bandpass Filter B1 LSB Register (offset = 0x93) [reset = 0]
7.6.2.2
Bandpass Filter Coefficient A2 (BPF_A2) Registers
7.6.2.2.1
Bandpass Filter Coefficient A2 MSB Register (offset = 0x94) [reset = 0]
7.6.2.2.2
Bandpass Filter Coefficient A2 LSB Register (offset = 0x95) [reset = 0]
7.6.2.3
Band-Pass Filter Coefficient A3 (BPF_A3) Register
7.6.2.3.1
Band-Pass Filter Coefficient A3 MSB Register (offset = 0x96) [reset = 0]
7.6.2.3.2
Band-Pass Filter Coefficient A3 LSB Register (offset = 0x97) [reset = 0]
7.6.2.4
Low-Pass Filter Coefficient B1 (LPF_B1) Registers
7.6.2.4.1
Low-Pass Filter Coefficient B1 MSB Register (offset = 0xA1) [reset = 0]
7.6.2.4.2
Low-Pass Filter Coefficient B1 LSB Register (offset = 0xA2) [reset = 0]
7.6.2.5
Low-Pass Filter Coefficient A2 (LPF_A2) Registers
7.6.2.5.1
Low-Pass Filter Coefficient A2 MSB Register (offset = 0xA3) [reset = 0]
7.6.2.5.2
Low-Pass Filter Coefficient A2 LSB Register (offset = 0xA4) [reset = 0]
7.6.2.6
Downsample Register (offset = 0xA5) [reset = 0]
7.6.2.7
BURST ON A Duration (ON_A) Registers
7.6.2.7.1
BURST ON A Duration MSB Register (offset = 0xA6) [reset = 0]
7.6.2.7.2
BURST ON A Duration LSB Register (offset = 0xA7) [reset = 0]
7.6.2.8
BURST OFFA Duration (OFF_A) Register
7.6.2.8.1
BURST OFFA Duration MSB Register (offset = 0xA9) [reset = 0]
7.6.2.8.2
BURST OFFA Duration LSB Register (offset = 0xAA) [reset = 0]
7.6.2.9
BURST ON B Duration (ON_B) Registers
7.6.2.9.1
BURST ON B Duration MSB Register (offset = 0xAB) [reset = 0]
7.6.2.9.2
BURST ON B Duration LSB Register (offset = 0xAC) [reset = 0]
7.6.2.10
BURST OFF B Duration (OFF_B) Register
7.6.2.10.1
BURST OFF B Duration MSB Register (offset = 0xAD) [reset = 0]
7.6.2.10.2
BURST OFF B Duration LSB Register (offset = 0xAE) [reset = 0]
7.6.2.11
Pulse Count A Register (offset = 0xAF) [reset = 0]
7.6.2.12
Pulse Count B Register (offset = 0xB1) [reset = 0]
7.6.2.13
Deadtime Register (offset = 0xB2) [reset = 0]
7.6.2.14
Burst Mode Register (offset = 0xB3) [reset = 0]
7.6.2.15
Temperature Sensor Register (offset = 0xB4) [reset = 0]
7.6.2.16
Saturation Deglitch Time Register (offset = 0xB5) [reset = 0]
7.6.2.17
Saturation Time Capture Register (offset = 0xB6) [reset = 0]
7.6.2.18
Control 1 Register (offset = 0xB7) [reset = 0]
7.6.2.19
Blanking Timer Register (offset = 0xB9) [reset = 0]
7.6.2.20
Free Running Timer (FRT) Registers
7.6.2.20.1
Free Running Timer MSB Registers (offset = 0xBA) [reset = 0]
7.6.2.20.2
Free Running Timer LSB Registers (offset = 0xBB) [reset = 0]
7.6.2.21
GPIO Control Register (offset = 0xBC) [reset = 0]
7.6.2.22
Clock Select Register (offset = 0xBD) [reset = 0]
7.6.2.23
Watchdog Enable Register (offset = 0xBE) [reset = 0]
7.6.2.24
LIN/SCI Select Register (offset = 0xBF) [reset = 0]
7.6.2.25
EEPROM Control Register (offset = 0xC0) [reset = 0]
7.6.2.26
Status 1 (STATUS1) Register (offset = 0xC1) [reset = 0]
7.6.2.27
Status 2 Register (offset = 0xC2) [reset = 0]
7.6.2.28
Power Mode Register (offset = 0xC3) [reset = 0]
7.6.2.29
Datapath and SCI Control Register (offset = 0xC4) [reset = 0]
7.6.2.30
FIFO Control Register (offset = 0xC5) [reset = ]
7.6.2.31
Enable Control Register (offset = 0xC8) [reset = 0]
7.6.2.32
LIN/SCI Rx Data (RX_DATAx) Register (offset = 0xC9 to 0xD1) [reset = 0]
7.6.2.33
LIN PID Register (offset = 0xD2) [reset = 0]
7.6.2.34
LIN/SCI Tx Data Registers (offset = 0xD3 to 0xDA) [reset = 0]
7.6.2.35
LIN/SCI Data Count Register (offset = 0xDB) [reset = 0]
7.6.2.36
LIN Configuration Register (offset = 0xDC) [reset = 0x40]
7.6.2.37
LIN Control Register (offset = 0xDD) [reset = 0]
7.6.2.38
LIN STATUS Register (offset = 0xDE) [reset = 0]
7.6.2.39
FIFO Pointer (FIFO_POINTER) Registers
7.6.2.39.1
FIFO Pointer MSB Register (offset = 0xDF) [reset = 0]
7.6.2.39.2
FIFO Pointer LSB Register (offset = 0xE1) [reset = 0]
7.6.2.40
VREG Select Register (offset = 0xE2) [reset = 0]
7.6.2.41
Sync Count (SYNC_COUNT) Registers
7.6.2.41.1
Sync Count MSB Register (offset = 0xE3) [reset = 0]
7.6.2.41.2
Sync Count LSB Register (offset = 0xE4) [reset = 0]
7.6.2.42
TEMP/DAC Control Register (offset = 0xE5) [reset = 0]
7.6.2.43
Oscillator Sync Control Register (offset = 0xE6) [reset = 0]
7.6.3
TEST Registers
7.6.3.1
ANALOG Test MUX Register (offset = 0xE9) [reset = 0]
7.6.3.2
DIGITAL Test MUX Register (offset = 0xEA) [reset = 0]
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Parameters
8.2.2
Detailed Design Procedure
8.2.2.1
Hardware
8.2.2.2
Firmware
8.2.2.2.1
Band-pass Filter Coefficients
8.2.2.2.2
Downsample Rate
8.2.2.2.3
Low-Pass Filter Coefficients
8.2.2.2.4
Pulse Count
8.2.2.2.5
Blanking Timer
8.2.2.2.6
FIFO Mode
8.2.2.3
OUT_A and OUT_B On and Off Times
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Community Resource
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PW|28
MPDS364
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slds185d_oa