SLASEJ4A April 2017  – August 2017 PGA460

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Internal Supply Regulators Characteristics
    6. 6.6 Transducer Driver Characteristics
    7. 6.7 Transducer Receiver Characteristics
    8. 6.8 Analog to Digital Converter Characteristics
    9. 6.9 Digital Signal Processing Characteristics
    10. 6.10Temperature Sensor Characteristics
    11. 6.11High-Voltage I/O Characteristics
    12. 6.12Digital I/O Characteristics
    13. 6.13EEPROM Characteristics
    14. 6.14Timing Requirements
    15. 6.15Switching Characteristics
    16. 6.16Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1 Power-Supply Block
      2. 7.3.2 Burst Generation
        1. 7.3.2.1Using Center-Tap Transformer
        2. 7.3.2.2Direct Drive
        3. 7.3.2.3Other Configurations
      3. 7.3.3 Analog Front-End
      4. 7.3.4 Digital Signal Processing
        1. 7.3.4.1Ultrasonic Echo—Band-Pass Filter
        2. 7.3.4.2Ultrasonic Echo-Rectifier, Peak Hold, Low-Pass Filter, and Data Selection
        3. 7.3.4.3Ultrasonic Echo—Nonlinear Scaling
        4. 7.3.4.4Ultrasonic Echo—Threshold Data Assignment
        5. 7.3.4.5Digital Gain
      5. 7.3.5 System Diagnostics
        1. 7.3.5.1Device Internal Diagnostics
      6. 7.3.6 Interface Description
        1. 7.3.6.1Time-Command Interface
          1. 7.3.6.1.1RUN Commands
          2. 7.3.6.1.2CONFIGURATION/STATUS Command
        2. 7.3.6.2USART Interface
          1. 7.3.6.2.1USART Asynchronous Mode
            1. 7.3.6.2.1.1Sync Field
            2. 7.3.6.2.1.2Command Field
            3. 7.3.6.2.1.3Data Fields
            4. 7.3.6.2.1.4Checksum Field
            5. 7.3.6.2.1.5PGA460 UART Commands
            6. 7.3.6.2.1.6UART Operations
              1. 7.3.6.2.1.6.1No-Response Operation
              2. 7.3.6.2.1.6.2Response Operation (All Except Register Read)
              3. 7.3.6.2.1.6.3Response Operation (Register Read)
            7. 7.3.6.2.1.7Diagnostic Field
            8. 7.3.6.2.1.8USART Synchronous Mode
          2. 7.3.6.2.2One-Wire UART Interface
          3. 7.3.6.2.3Ultrasonic Object Detection Through UART Operations
        3. 7.3.6.3In-System IO-Pin Interface Selection
      7. 7.3.7 Echo Data Dump
        1. 7.3.7.1On-Board Memory Data Store
        2. 7.3.7.2Direct Data Burst Through USART Synchronous Mode
      8. 7.3.8 Low-Power Mode
        1. 7.3.8.1Time-Command Interface
        2. 7.3.8.2UART Interface
      9. 7.3.9 Transducer Time and Temperature Decoupling
        1. 7.3.9.1Time Decoupling
        2. 7.3.9.2Temperature Decoupling
      10. 7.3.10Memory CRC Calculation
      11. 7.3.11Temperature Sensor and Temperature Data-Path
      12. 7.3.12TEST Pin Functionality
    4. 7.4Device Functional Modes
    5. 7.5Programming
      1. 7.5.1UART and USART Communication Examples
    6. 7.6Register Maps
      1. 7.6.1EEPROM Programming
      2. 7.6.2Register Map Partitioning and Default Values
      3. 7.6.3REGMAP Registers
        1. 7.6.3.1 USER_DATA1 Register (Address = 0h) [reset = 0h]
        2. 7.6.3.2 USER_DATA2 Register (Address = 1h) [reset = 0h]
        3. 7.6.3.3 USER_DATA3 Register (Address = 2h) [reset = 0h]
        4. 7.6.3.4 USER_DATA4 Register (Address = 3h) [reset = 0h]
        5. 7.6.3.5 USER_DATA5 Register (Address = 4h) [reset = 0h]
        6. 7.6.3.6 USER_DATA6 Register (Address = 5h) [reset = 0h]
        7. 7.6.3.7 USER_DATA7 Register (Address = 6h) [reset = 0h]
        8. 7.6.3.8 USER_DATA8 Register (Address = 7h) [reset = 0h]
        9. 7.6.3.9 USER_DATA9 Register (Address = 8h) [reset = 0h]
        10. 7.6.3.10USER_DATA10 Register (Address = 9h) [reset = 0h]
        11. 7.6.3.11USER_DATA11 Register (Address = Ah) [reset = 0h]
        12. 7.6.3.12USER_DATA12 Register (Address = Bh) [reset = 0h]
        13. 7.6.3.13USER_DATA13 Register (Address = Ch) [reset = 0h]
        14. 7.6.3.14USER_DATA14 Register (Address = Dh) [reset = 0h]
        15. 7.6.3.15USER_DATA15 Register (Address = Eh) [reset = 0h]
        16. 7.6.3.16USER_DATA16 Register (Address = Fh) [reset = 0h]
        17. 7.6.3.17USER_DATA17 Register (Address = 10h) [reset = 0h]
        18. 7.6.3.18USER_DATA18 Register (Address = 11h) [reset = 0h]
        19. 7.6.3.19USER_DATA19 Register (Address = 12h) [reset = 0h]
        20. 7.6.3.20USER_DATA20 Register (Address = 13h) [reset = 0h]
        21. 7.6.3.21TVGAIN0 Register (Address = 14h) [reset = 0h]
        22. 7.6.3.22TVGAIN1 Register (Address = 15h) [reset = 0h]
        23. 7.6.3.23TVGAIN2 Register (Address = 16h) [reset = 0h]
        24. 7.6.3.24TVGAIN3 Register (Address = 17h) [reset = 0h]
        25. 7.6.3.25TVGAIN4 Register (Address = 18h) [reset = 0h]
        26. 7.6.3.26TVGAIN5 Register (Address = 19h) [reset = 0h]
        27. 7.6.3.27TVGAIN6 Register (Address = 1Ah) [reset = 0h]
        28. 7.6.3.28INIT_GAIN Register (Address = 1Bh) [reset = 0h]
        29. 7.6.3.29FREQUENCY Register (Address = 1Ch) [reset = 0h]
        30. 7.6.3.30DEADTIME Register (Address = 1Dh) [reset = 0h]
        31. 7.6.3.31PULSE_P1 Register (Address = 1Eh) [reset = 0h]
        32. 7.6.3.32PULSE_P2 Register (Address = 1Fh) [reset = 0h]
        33. 7.6.3.33CURR_LIM_P1 Register (Address = 20h) [reset = 0h]
        34. 7.6.3.34CURR_LIM_P2 Register (Address = 21h) [reset = 0h]
        35. 7.6.3.35REC_LENGTH Register (Address = 22h) [reset = 0h]
        36. 7.6.3.36FREQ_DIAG Register (Address = 23h) [reset = 0h]
        37. 7.6.3.37SAT_FDIAG_TH Register (Address = 24h) [reset = 0h]
        38. 7.6.3.38FVOLT_DEC Register (Address = 25h) [reset = 0h]
        39. 7.6.3.39DECPL_TEMP Register (Address = 26h) [reset = 0h]
        40. 7.6.3.40DSP_SCALE Register (Address = 27h) [reset = 0h]
        41. 7.6.3.41TEMP_TRIM Register (Address = 28h) [reset = 0h]
        42. 7.6.3.42P1_GAIN_CTRL Register (Address = 29h) [reset = 0h]
        43. 7.6.3.43P2_GAIN_CTRL Register (Address = 2Ah) [reset = 0h]
        44. 7.6.3.44EE_CRC Register (Address = 2Bh) [reset = 0h]
        45. 7.6.3.45EE_CNTRL Register (Address = 40h) [reset = 00h]
        46. 7.6.3.46BPF_A2_MSB Register (Address = 41h) [reset = 00h]
        47. 7.6.3.47BPF_A2_LSB Register (Address = 42h) [reset = 00h]
        48. 7.6.3.48BPF_A3_MSB Register (Address = 43h) [reset = 00h]
        49. 7.6.3.49BPF_A3_LSB Register (Address = 44h) [reset = 00h]
        50. 7.6.3.50BPF_B1_MSB Register (Address = 45h) [reset = 00h]
        51. 7.6.3.51BPF_B1_LSB Register (Address = 46h) [reset = 00h]
        52. 7.6.3.52LPF_A2_MSB Register (Address = 47h) [reset = 00h]
        53. 7.6.3.53LPF_A2_LSB Register (Address = 48h) [reset = 00h]
        54. 7.6.3.54LPF_B1_MSB Register (Address = 49h) [reset = 00h]
        55. 7.6.3.55LPF_B1_LSB Register (Address = 4Ah) [reset = 00h]
        56. 7.6.3.56TEST_MUX Register (Address = 4Bh) [reset = 00h]
        57. 7.6.3.57DEV_STAT0 Register (Address = 4Ch) [reset = 84h]
        58. 7.6.3.58DEV_STAT1 Register (Address = 4Dh) [reset = 00h]
        59. 7.6.3.59P1_THR_0 Register (Address = 5Fh) [reset = X]
        60. 7.6.3.60P1_THR_1 Register (Address = 60h) [reset = X]
        61. 7.6.3.61P1_THR_2 Register (Address = 61h) [reset = X]
        62. 7.6.3.62P1_THR_3 Register (Address = 62h) [reset = X]
        63. 7.6.3.63P1_THR_4 Register (Address = 63h) [reset = X]
        64. 7.6.3.64P1_THR_5 Register (Address = 64h) [reset = X]
        65. 7.6.3.65P1_THR_6 Register (Address = 65h) [reset = X]
        66. 7.6.3.66P1_THR_7 Register (Address = 66h) [reset = X]
        67. 7.6.3.67P1_THR_8 Register (Address = 67h) [reset = X]
        68. 7.6.3.68P1_THR_9 Register (Address = 68h) [reset = X]
        69. 7.6.3.69P1_THR_10 Register (Address = 69h) [reset = X]
        70. 7.6.3.70P1_THR_11 Register (Address = 6Ah) [reset = X]
        71. 7.6.3.71P1_THR_12 Register (Address = 6Bh) [reset = X]
        72. 7.6.3.72P1_THR_13 Register (Address = 6Ch) [reset = X]
        73. 7.6.3.73P1_THR_14 Register (Address = 6Dh) [reset = X]
        74. 7.6.3.74P1_THR_15 Register (Address = 6Eh) [reset = X]
        75. 7.6.3.75P2_THR_0 Register (Address = 6Fh) [reset = X]
        76. 7.6.3.76P2_THR_1 Register (Address = 70h) [reset = X]
        77. 7.6.3.77P2_THR_2 Register (Address = 71h) [reset = X]
        78. 7.6.3.78P2_THR_3 Register (Address = 72h) [reset = X]
        79. 7.6.3.79P2_THR_4 Register (Address = 73h) [reset = X]
        80. 7.6.3.80P2_THR_5 Register (Address = 74h) [reset = X]
        81. 7.6.3.81P2_THR_6 Register (Address = 75h) [reset = X]
        82. 7.6.3.82P2_THR_7 Register (Address = 76h) [reset = X]
        83. 7.6.3.83P2_THR_8 Register (Address = 77h) [reset = X]
        84. 7.6.3.84P2_THR_9 Register (Address = 78h) [reset = X]
        85. 7.6.3.85P2_THR_10 Register (Address = 79h) [reset = X]
        86. 7.6.3.86P2_THR_11 Register (Address = 7Ah) [reset = X]
        87. 7.6.3.87P2_THR_12 Register (Address = 7Bh) [reset = X]
        88. 7.6.3.88P2_THR_13 Register (Address = 7Ch) [reset = X]
        89. 7.6.3.89P2_THR_14 Register (Address = 7Dh) [reset = X]
        90. 7.6.3.90P2_THR_15 Register (Address = 7Eh) [reset = X]
        91. 7.6.3.91THR_CRC Register (Address = 7Fh) [reset = X]
  8. Application and Implementation
    1. 8.1Application Information
      1. 8.1.1Transducer Types
    2. 8.2Typical Applications
      1. 8.2.1Transformer-Driven Method
        1. 8.2.1.1Design Requirements
        2. 8.2.1.2Detailed Design Procedure
          1. 8.2.1.2.1Transducer Driving Voltage
          2. 8.2.1.2.2Transducer Pulse Count
          3. 8.2.1.2.3Transformer Turns Ratio
          4. 8.2.1.2.4Transformer Saturation Current and Main Voltage Rating
        3. 8.2.1.3Application Curves
      2. 8.2.2Direct-Driven (Transformer-Less) Method
        1. 8.2.2.1Design Requirements
        2. 8.2.2.2Detailed Design Procedure
        3. 8.2.2.3Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Documentation Support
      1. 11.1.1Related Documentation
    2. 11.2Receiving Notification of Documentation Updates
    3. 11.3Community Resources
    4. 11.4Trademarks
    5. 11.5Electrostatic Discharge Caution
    6. 11.6Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Features

  • Fully Integrated Solution for Ultrasonic Sensing
  • Complimentary Low-Side Drivers With Configurable Current Limit Supporting Both Transformer Based and Direct Drive Topology for Transducer Excitation
  • Single Transducer for Both Burst/Listen or a Transducer Pair, One for Burst and the Other for Listen Operation
  • Low-Noise Receiver With Programmable 6-Point Time-Varying Gain (32 to 90 dB) With DSP (BPF, Demodulation) for Echo Envelope Detection
  • Two Presets of 12-Point Time-Varying Threshold for Object Detection
  • Timers to Measure Multiple Echo Distance and Duration
  • Integrated Temperature Sensor
  • Record Time for Object Detection up to 11 m
  • 128 Bytes of RAM for Echo Recording
  • 42 Bytes of User EEPROM to Store Configuration for Fast Initialization
  • One-Wire High-Voltage Time-Command Interface or USART Asynchronous Interface
  • CMOS Level USART Interface
  • Sensor Diagnostics (Decay Frequency and Time, Excitation Voltage), Supply, and Transceiver Diagnostics.

Applications

  • Ultrasonic Radar
  • Object distance and Position Sensing
  • Presence and Proximity Detection
  • Drone and Robotics Landing Assist and Obstacle Detection
  • Occupancy and Motion Sensors

Description

The PGA460 device is a highly-integrated system on-chip ultrasonic transducer driver and signal conditioner with an advanced DSP core. The device has a complimentary low-side driver pair that can drive a transducer either in a transformer based topology using a step-up transformer or in a direct-drive topology using external high-side FETs. The device can receive and condition the reflected echo signal for reliable object detection. This feature is accomplished using an analog front-end (AFE) consisting of a low-noise amplifier followed by a programmable time-varying gain stage feeding into an ADC. The digitized signal is processed in the DSP core for both near-field and far-field object detection using time-varying thresholds.

The main communication with an external controller is achieved by either a time-command interface (TCI) or a one-wire USART asynchronous interface on the IO pin, or a CMOS-level USART interface on the RXD and TXD pins. The PGA460 can be put in ultra-low quiescent current low-power mode to reduce power consumption when not in use and can be woken up by commands on the communication interfaces.

The PGA460 also includes on-chip system diagnostics which monitor transducer voltage during burst, frequency and decay time of transducer to provide information about the integrity of the excitation as well as supply-side and transceiver-side diagnostics for overvoltage, undervoltage, overcurrent and short-circuit scenarios.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
PGA460TSSOP (16)5.00 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Diagram (Transformer Drive)

PGA460 alt_slasec8.gif

Revision History

Changes from * Revision (April 2017) to A Revision

  • Added zero padding information to the CONFIGURATION/STATUS Command sectionGo
  • Changed UART interface parameter text from: 1 stop bit to: 2 stop bit Go
  • Changed interfield wait time text from: optional to: required for 1 stop bitGo
  • Added sentence: The sync field (0x55) is not included as part of the checksum calculation.Go
  • Updated content and added tablenotes to Table 3Go
  • Added sentence: The diagnostic field is included in the slave generated checksum calculation. Go
  • Added subsection Direct Data Burst Through USART Synchronous ModeGo
  • Added Equation 8Go
  • Added sentence: This includes all threshold timing and level values. Go
  • Updated UART and USART Communication Examples contentGo
  • Updated content in Table 101 Go
  • Added content to Application CurvesGo
  • Added content to Direct-Driven (Transformer-Less) Method and changed Figure 141 such that a GND node is present at XDCRNegative and CINN Go
  • Changed text from: TDK EPCOS B78416A2232A03 Transformer, muRata MA40H1S-R transducer to: Fairchild FDC6506P p-channel MOSFET, muRata MA40H1S-R transducerGo