SLDS209A January 2015  – May 2015 PGA900

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Gate Drive
    6. 6.6 Reverse Voltage Protection
    7. 6.7 Regulators
    8. 6.8 Internal Reference
    9. 6.9 Internal Oscillator
    10. 6.10Bridge Sensor Supply
    11. 6.11Temperature Sensor Supply
    12. 6.12Internal Temperature Sensor
    13. 6.13P Gain (Chopper Stabilized)
    14. 6.14P Analog-to-Digital Converter
    15. 6.15T Gain (Chopper Stabilized)
    16. 6.16T Analog-to-Digital Converter
    17. 6.17OWI
    18. 6.18SPI
    19. 6.19I2C Interface
    20. 6.20PWM Output
    21. 6.21DAC Output
    22. 6.22DAC Gain
    23. 6.23GPIO, Digital Test In / Test Out, UART TX/RX Buffers
    24. 6.24Non-Volatile Memory
    25. 6.25Diagnostics
    26. 6.26M0
    27. 6.27OWI Timing Requirements
    28. 6.28SPI Timing Requirements
    29. 6.29I2C Interface Timing Requirements
    30. 6.30Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1 Gate Drive for N-Channel Depletion NMOS
      2. 7.3.2 Reverse Voltage Protection Block
      3. 7.3.3 Linear Regulators
      4. 7.3.4 Internal Reference
        1. 7.3.4.1Inaccurate Reference
        2. 7.3.4.2Accurate Reference
      5. 7.3.5 Internal Oscillator
      6. 7.3.6 VBRGP/VBRGN Supply for Resistive Bridge
      7. 7.3.7 ITEMP Supply for Temperature Sensor
      8. 7.3.8 Internal Temperature Sensor
      9. 7.3.9 P Gain
      10. 7.3.10P Analog-to-Digital Converter
        1. 7.3.10.1P Sigma Delta Modulator for P ADC
        2. 7.3.10.2P Decimation Filter for P ADC
        3. 7.3.10.3P ADC Configuration
        4. 7.3.10.4Connecting P GAIN Output to P ADC Input
      11. 7.3.11T Gain
      12. 7.3.12T Analog-to-Digital Converter
        1. 7.3.12.1T Sigma-Delta Modulator for T ADC
        2. 7.3.12.2T Decimation Filters for T ADC
          1. 7.3.12.2.1T ADC Configuration
        3. 7.3.12.3Connecting T GAIN Output to T ADC Input
      13. 7.3.13Digital Interfaces
        1. 7.3.13.1Accessing PGA900 Memories while Microprocessor is Running
          1. 7.3.13.1.1COMBUF Register Data Coherency
            1. 7.3.13.1.1.1Coherency for Transfer from PGA900 to Master
            2. 7.3.13.1.1.2Coherency for Transfer from Master to PGA900
        2. 7.3.13.2Accessing PGA900 Memories While Microprocessor is in Reset
        3. 7.3.13.3Accessing OTP, DEVRAM, and DATARAM Using 8-Bit Addresses
      14. 7.3.14OWI
        1. 7.3.14.1Overview of OWI
        2. 7.3.14.2Activating and Deactivating the OWI
          1. 7.3.14.2.1Activating OWI Communication
          2. 7.3.14.2.2Deactivating OWI Communication
        3. 7.3.14.3OWI Protocol
          1. 7.3.14.3.1OWI Frame Structure
            1. 7.3.14.3.1.1Standard Field Structure
            2. 7.3.14.3.1.2Frame Structure
            3. 7.3.14.3.1.3Sync Field
            4. 7.3.14.3.1.4Command Field
            5. 7.3.14.3.1.5Data Fields
          2. 7.3.14.3.2OWI Commands
            1. 7.3.14.3.2.1OWI Write Command
            2. 7.3.14.3.2.2OWI Read Initialization Command
            3. 7.3.14.3.2.3OWI Read Response Command
            4. 7.3.14.3.2.4OWI Burst Write Command (EEPROM Cache Access)
            5. 7.3.14.3.2.5OWI Burst Read Command (EEPROM Cache Access)
          3. 7.3.14.3.3OWI Operations
            1. 7.3.14.3.3.1Write Operation
            2. 7.3.14.3.3.2Read Operation
            3. 7.3.14.3.3.3EEPROM Burst Write
            4. 7.3.14.3.3.4EEPROM Burst Read
        4. 7.3.14.4OWI Communication Error Status
      15. 7.3.15SPI
        1. 7.3.15.1Overview of SPI
        2. 7.3.15.2Activating the SPI
        3. 7.3.15.3SPI Protocol
          1. 7.3.15.3.1SPI Master to PGA900 Commands
          2. 7.3.15.3.2PGA900 to SPI Master Response
          3. 7.3.15.3.3SPI Command Examples
        4. 7.3.15.4Clocking Details of SPI
      16. 7.3.16I2C Interface
        1. 7.3.16.1Overview of I2C Interface
        2. 7.3.16.2Activating the I2C Interface
        3. 7.3.16.3I2C Interface Protocol
        4. 7.3.16.4Clocking Details of I2C Interface
      17. 7.3.17PWM Logic
        1. 7.3.17.1PWM Logic Enable
        2. 7.3.17.2PWM ON and OFF Times
        3. 7.3.17.3PWM Voltage Levels
      18. 7.3.18DAC Output
        1. 7.3.18.1Ratiometric versus Absolute
      19. 7.3.19DAC Gain
        1. 7.3.19.1Connecting DAC Output to DAC GAIN Input
      20. 7.3.20General-Purpose Input/Output (GPIO) and UART
        1. 7.3.20.1GPIO
        2. 7.3.20.2UART
      21. 7.3.21Memory
        1. 7.3.21.1OTP Memory
          1. 7.3.21.1.1OTP Programming Using SPI
        2. 7.3.21.2OTP Programming Using I2C
        3. 7.3.21.3EEPROM Memory
          1. 7.3.21.3.1EEPROM Cache
          2. 7.3.21.3.2EEPROM Programming Procedure
          3. 7.3.21.3.3EEPROM Programming Current
          4. 7.3.21.3.4CRC
        4. 7.3.21.4DATA RAM Memory
        5. 7.3.21.5Control and Status Registers Memory
        6. 7.3.21.6Software Development RAM
          1. 7.3.21.6.1Software Development
            1. 7.3.21.6.1.1Downloading Software into Development RAM Using Digital Interface
          2. 7.3.21.6.2Trace FIFO
        7. 7.3.21.7OTP Security
          1. 7.3.21.7.1Definition of OTP Security
          2. 7.3.21.7.2OTP Security in PGA900
          3. 7.3.21.7.3Enabling OTP Security in PGA900
          4. 7.3.21.7.4Using OTP Security in PGA900
          5. 7.3.21.7.5Sequence in Manufacturing Line
      22. 7.3.22Diagnostics
        1. 7.3.22.1Power Supply Diagnostics
        2. 7.3.22.2Resistive Bridge Sensor and Temperature Sensor Connectivity Diagnostics
          1. 7.3.22.2.1P Gain Input Faults
          2. 7.3.22.2.2T Gain Input Faults
        3. 7.3.22.3P Gain and T Gain Output Diagnostics
        4. 7.3.22.4DAC Diagnostics
        5. 7.3.22.5Harness Open Wire Diagnostics
        6. 7.3.22.6Software Watchdog
        7. 7.3.22.7EEPROM CRC and TRIM Error
        8. 7.3.22.8DATA RAM MBIST
        9. 7.3.22.9Development RAM MBIST
      23. 7.3.23ARM Cortex-M0 Microprocessor
        1. 7.3.23.1SYSTICK Timer
        2. 7.3.23.2NVIC Controller
        3. 7.3.23.3Software Debugger
      24. 7.3.24Revision ID
      25. 7.3.25Test MUX
    4. 7.4Device Functional Modes
      1. 7.4.1Voltage Mode
      2. 7.4.2Current Mode
    5. 7.5Register Maps
      1. 7.5.1Memory Map
      2. 7.5.2Control and Status Registers
        1. 7.5.2.1 RAM MBIST Control (M0 address = 0x40000502) (DI page address = 0x2) (DI page offset = 0x02)
        2. 7.5.2.2 RAM MBIST Status (M0 address = 0x40000503) (DI page address = 0x2) (DI page offset = 0x03)
        3. 7.5.2.3 M0 Frequency Control (M0 address = 0x40000504) (DI page address = 0x2) (DI page offset = 0x04)
        4. 7.5.2.4 Digital Interface Control (M0 address = 0x40000506) (DI page address = 0x2) (DI page offset = 0x06)
        5. 7.5.2.5 OWI_ERROR_STATUS_LO (M0 address = 0x40000508) (DI page address = 0x2) (DI page offset = 0x08)
        6. 7.5.2.6 OWI_ERROR_STATUS_HI (M0 address = 0x40000509) (DI page address = 0x2) (DI page offset = 0x09)
        7. 7.5.2.7 OWI_INTERRUPT (M0 address = 0x4000050A) (DI page address = 0x2) (DI page offset = 0x0A)
        8. 7.5.2.8 OWI_INTERRUPT_EN (M0 address = 0x4000050B) (DI page address = 0x2) (DI page offset = 0x0B)
        9. 7.5.2.9 OTP_PROG_DATA1-4
        10. 7.5.2.10OTP_PROG_ADDR1-2
        11. 7.5.2.11OTP_PROG_CTRL_STAT (M0 address = 0x40000516) (DI page address = 0x2) (DI page offset = 0x16)
        12. 7.5.2.12OTP_PAGE_ADDR (M0 address = 0x40000518) (DI page address = 0x2) (DI page offset = 0x18)
        13. 7.5.2.13DATARAM_PAGE_ADDR (M0 address = 0x40000519) (DI page address = 0x2) (DI page offset = 0x19)
        14. 7.5.2.14DEVRAM_PAGE_ADDR (M0 address = 0x4000051A) (DI page address = 0x2) (DI page offset = 0x1A)
        15. 7.5.2.15WDOG_CTRL_STAT (M0 address = 0x4000051C) (DI page address = 0x2) (DI page offset = 0x1C)
        16. 7.5.2.16WDOG_TRIG (M0 address = 0x4000051D) (DI page address = 0x2) (DI page offset = 0x1D)
        17. 7.5.2.17PIN_MUX (M0 address = 0x4000051E) (DI page address = 0x2) (DI page offset = 0x1E)
        18. 7.5.2.18PADC_DATA1-3
        19. 7.5.2.19PADC_CONFIG (M0 address = 0x40000523) (DI page address = 0x2) (DI page offset = 0x23)
        20. 7.5.2.20TADC_DATA1-3
        21. 7.5.2.21TADC_CONFIG (M0 address = 0x40000527) (DI page address = 0x2) (DI page offset = 0x27)
        22. 7.5.2.22ADC_CFG_1 (M0 address = 0x40000529) (DI page address = 0x2) (DI page offset = 0x29)
        23. 7.5.2.23DAC_REG
        24. 7.5.2.24DAC_CTRL_STATUS (M0 address = 0x40000538) (DI page address = 0x2) (DI page offset = 0x38)
        25. 7.5.2.25DAC_CONFIG (M0 address = 0x40000539) (DI page address = 0x2) (DI page offset = 0x39)
        26. 7.5.2.26DAC_LPBK_CTRL (M0 address = 0x4000053A) (DI page address = 0x2) (DI page offset = 0x3A)
        27. 7.5.2.27OP_STAGE_CTRL (M0 address = 0x4000053B) (DI page address = 0x2) (DI page offset = 0x3B)
        28. 7.5.2.28AFE_CFG (M0 address = 0x400004F4) (DI page address = 0x0) (DI page offset = 0xF4)
        29. 7.5.2.29AFEDIAG_CFG (M0 address = 0x40000545) (DI page address = 0x2) (DI page offset = 0x45)
        30. 7.5.2.30BRDG_CTRL (M0 address = 0x40000546) (DI page address = 0x2) (DI page offset = 0x46)
        31. 7.5.2.31P_GAIN_SELECT (M0 address = 0x40000547) (DI page address = 0x2) (DI page offset = 0x47)
        32. 7.5.2.32T_GAIN_SELECT (M0 address = 0x40000548) (DI page address = 0x2) (DI page offset = 0x48)
        33. 7.5.2.33TEMP_CTRL (M0 address = 0x4000054C) (DI page address = 0x2) (DI page offset = 0x4C)
        34. 7.5.2.34ALPWR (M0 address = 0x40000550) (DI page address = 0x2) (DI page offset = 0x50)
        35. 7.5.2.35DLPWR (M0 address = 0x40000554) (DI page address = 0x2) (DI page offset = 0x54)
        36. 7.5.2.36PSMON1 (M0 address = 0x40000558) (DI page address = 0x2) (DI page offset = 0x58)
        37. 7.5.2.37PSMON2 (M0 address = 0x40000559) (DI page address = 0x2) (DI page offset = 0x59)
        38. 7.5.2.38AFEDIAG (M0 address = 0x4000055A) (DI page address = 0x2) (DI page offset = 0x5A)
        39. 7.5.2.39TOPDIG_MUX_SEL (M0 address = 0x40000560) (DI page address = 0x2) (DI page offset = 0x60)
        40. 7.5.2.40TONDIG_MUX_SEL (M0 address = 0x40000561) (DI page address = 0x2) (DI page offset = 0x61)
        41. 7.5.2.41AMUX_ACT (M0 address = 0x40000564) (DI page address = 0x2) (DI page offset = 0x64)
        42. 7.5.2.42AMUX_TIN_MUX_CTRL (M0 address = 0x40000565) (DI page address = 0x2) (DI page offset = 0x65)
        43. 7.5.2.43AMUX_TOUT_MUX_CTRL (M0 address = 0x40000566) (DI page address = 0x2) (DI page offset = 0x66)
        44. 7.5.2.44AMUX_CTRL (M0 address = 0x40000567) (DI page address = 0x2) (DI page offset = 0x67)
        45. 7.5.2.45TRACE_FIFO_CTRL_STAT (M0 address = 0x40000570) (DI page address = 0x2) (DI page offset = 0x70)
        46. 7.5.2.46REVISION_ID1 (M0 address = 0x40000400) (DI page address = 0x0) (DI page offset = 0x00)
        47. 7.5.2.47REVISION_ID2 (M0 address = 0x40000401) (DI page address = 0x0) (DI page offset = 0x01)
        48. 7.5.2.48COM_MCU_TO_DIF_B1 (M0 address = 0x40000404) (DI page address = 0x0) (DI page offset = 0x04)
        49. 7.5.2.49COM_MCU_TO_DIF_B2 (M0 address = 0x40000405) (DI page address = 0x0) (DI page offset = 0x05)
        50. 7.5.2.50COM_TX_STATUS (M0 address = 0x40000406) (DI page address = 0x0) (DI page offset = 0x06)
        51. 7.5.2.51COM_DIF_TO_MCU_B1 (M0 address = 0x40000408) (DI page address = 0x0) (DI page offset = 0x08)
        52. 7.5.2.52COM_DIF_TO_MCU_B2 (M0 address = 0x40000409) (DI page address = 0x0) (DI page offset = 0x09)
        53. 7.5.2.53COM_RX_STATUS (M0 address = 0x4000040A) (DI page address = 0x0) (DI page offset = 0x0A)
        54. 7.5.2.54COM_RX_INT_ENABLE (M0 address = 0x4000040B) (DI page address = 0x0) (DI page offset = 0x0B)
        55. 7.5.2.55MICRO_INTERFACE_CONTROL (M0 address = 0x4000040C) (DI page address = 0x0) (DI page offset = 0x0C)
        56. 7.5.2.56SECLOCK (M0 address = 0x4000040D) (DI page address = 0x0) (DI page offset = 0x0D)
        57. 7.5.2.57UART_CFG (M0 address = 0x40000200) (DI page address = 0x7) (DI page offset = 0x00)
        58. 7.5.2.58UART_EN (M0 address = 0x40000201) (DI page address = 0x7) (DI page offset = 0x01)
        59. 7.5.2.59BAUD_RATE_LO (M0 address = 0x40000202) (DI page address = 0x7) (DI page offset = 0x02)
        60. 7.5.2.60BAUD_RATE_HI (M0 address = 0x40000203) (DI page address = 0x7) (DI page offset = 0x03)
        61. 7.5.2.61UART_LINE_STATUS (M0 address = 0x40000204) (DI page address = 0x7) (DI page offset = 0x04)
        62. 7.5.2.62UART_INTERRUPT_STATUS (M0 address = 0x40000208) (DI page address = 0x7) (DI page offset = 0x08)
        63. 7.5.2.63UART_INTERRUPT_ENABLE (M0 address = 0x4000020A) (DI page address = 0x7) (DI page offset = 0x0A)
        64. 7.5.2.64UART_RX_BUF (M0 address = 0x4000020C) (DI page address = 0x7) (DI page offset = 0x0C)
        65. 7.5.2.65UART_TX_BUF (M0 address = 0x4000020E) (DI page address = 0x7) (DI page offset = 0x0E)
        66. 7.5.2.66PWM_ON_TIME1-2
        67. 7.5.2.67PWM_OFF_TIME1-2
        68. 7.5.2.68PWM_EN (M0 address = 0x40000214) (DI page address = 0x7) (DI page offset = 0x14)
        69. 7.5.2.69GPIO_INPUT (M0 address = 0x40000218) (DI page address = 0x7) (DI page offset = 0x18)
        70. 7.5.2.70GPIO_OUTPUT (M0 address = 0x40000219) (DI page address = 0x7) (DI page offset = 0x19)
        71. 7.5.2.71GPIO_DIR (M0 address = 0x4000021A) (DI page address = 0x7) (DI page offset = 0x1A)
        72. 7.5.2.72REMAP (M0 address = 0x40000220) (DI page address = 0x7) (DI page offset = 0x20)
        73. 7.5.2.73EEPROM_PAGE_ADDRESS (M0 address = 0x40000088) (DI page address = 0x5) (DI page offset = 0x88)
        74. 7.5.2.74EEPROM_CTRL (M0 address = 0x40000089) (DI page address = 0x5) (DI page offset = 0x89)
        75. 7.5.2.75EEPROM_CRC (M0 address = 0x4000008A) (DI page address = 0x5) (DI page offset = 0x8A)
        76. 7.5.2.76EEPROM_STATUS (M0 address = 0x4000008B) (DI page address = 0x5) (DI page offset = 0x8B)
        77. 7.5.2.77EEPROM_CRC_STATUS (M0 address = 0x4000008C) (DI page address = 0x5) (DI page offset = 0x8C)
        78. 7.5.2.78EEPROM_CRC_VALUE (M0 address = 0x4000008D) (DI page address = 0x5) (DI page offset = 0x8D)
      3. 7.5.3Interrupt Sources
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.14- to 20-mA Output With Internal Sense Resistor
        1. 8.2.1.1Design Requirements
        2. 8.2.1.2Detailed Design Procedure
          1. 8.2.1.2.1Programmer Tips
            1. 8.2.1.2.1.1Resetting the Microprocessor and Enable Digital Interface
            2. 8.2.1.2.1.2Turning on Accurate Reference Buffer (REFCAP Voltage)
            3. 8.2.1.2.1.3Turning on DAC and DAC GAIN
        3. 8.2.1.3Application Curve
      2. 8.2.2Using External Depletion MOSFET when Supply to Sensor >30 V With GATE Control
        1. 8.2.2.1Design Requirements
        2. 8.2.2.2Detailed Design Procedure
          1. 8.2.2.2.1Programmer Tips
      3. 8.2.30- to 10-V Absolute Output With Internal Drive
        1. 8.2.3.1Design Requirements
        2. 8.2.3.2Detailed Design Procedure
          1. 8.2.3.2.1Programmer Tips
            1. 8.2.3.2.1.1Resetting the Microprocessor and Enable Digital Interface
            2. 8.2.3.2.1.2Turning on Accurate Reference Buffer (REFCAP Voltage)
            3. 8.2.3.2.1.3Turning on DAC and DAC GAIN
      4. 8.2.40- to 5-V Ratiometric Output With Internal Drive
        1. 8.2.4.1Design Requirements
        2. 8.2.4.2Detailed Design Procedure
          1. 8.2.4.2.1Programmer Tips
            1. 8.2.4.2.1.1Resetting the Microprocessor and Enable Digital Interface
            2. 8.2.4.2.1.2Turning on Accurate Reference Buffer (REFCAP Voltage)
            3. 8.2.4.2.1.3Turning on DAC and DAC GAIN
      5. 8.2.50- to 10-V PWM Output With Internal Drive
        1. 8.2.5.1Design Requirements
        2. 8.2.5.2Detailed Design Procedure
          1. 8.2.5.2.1Programmer Tips
            1. 8.2.5.2.1.1Resetting the Microprocessor and Enable Digital Interface
            2. 8.2.5.2.1.2Turning on Accurate Reference Buffer (REFCAP Voltage)
            3. 8.2.5.2.1.3Turning on DAC and DAC GAIN
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Community Resources
    2. 11.2Trademarks
    3. 11.3Electrostatic Discharge Caution
    4. 11.4Glossary
  12. 12Mechanical, Packaging, and Orderable Information

1 Features

  • High Accuracy, Low Noise, Low Power, Small Size Resistive Sensing Signal Conditioner
  • User-Programmable Temperature and Nonlinearity Compensation
  • On-Chip ARM®Cortex® M0 Microprocessor Allows Users to Develop and Implement Calibration Software
  • One-Wire Interface Enables the Communication through Power Supply Pin Without Using Additional Lines
  • On-Chip Power Management Accepts Wide Power Supply Voltage from 3.3 V to 30 V
  • Operating Temperature Range: –40°C to 150°C
  • Memory
    • 8 KB Software Memory
    • 128 Bytes EEPROM
    • 1 KB Data SRAM
  • Accommodates Sensor Sensitivities from 1 mV/V to 135 mV/ V
  • Two Individual Analog-Front End (AFE) Chains, each Including:
    • Low Noise Programmable Gain Amplifier
    • 24-bit Sigma-Delta Analog-to-Digital Converter
  • Built-in Internal Temperature Sensor With Option to Use External Temperature Sensor
  • 14-bit DAC With Programmable Gain Amplifier
  • Output Options:
    • Ratiometric and Absolute Voltage Output
    • 4- to 20-mA Current Loop Interface
    • One-Wire Interface (OWI) Over Power Line
    • PWM Output
    • Serial Peripheral Interface (SPI)
    • Inter-Integrated Circuit (I2C)
  • Depletion MOSFET Gate Driver
  • Diagnostic Functions

2 Applications

  • Pressure Sensor Transmitter, Transducer
  • Liquid Level Meter, Flow Meter
  • Weight Scale, Load Meter, Strain Gauge
  • Thermocouple, Thermistor, and 2-Wire Resistance Thermometer (RTD)
  • Resistive Field Transmitter

3 Description

The PGA900 is a signal conditioner for resistive sensing applications. It can accommodate various sensing element types. The PGA900 conditions its input signals by amplification and digitization through two analog front end channels. With the user programmed software in the on-chip ARM Cortex M0 processor, the PGA900 can perform linearization, temperature compensation, and other user defined compensation algorithms. The conditioned signal can be output as ratiometric voltage, absolute voltage, 4- to 20-mA current loop or PWM. The data and configuration registers can also be accessed through SPI, I2C, UART, and two GPIO ports. In addition, the unique OWI allows communication and configuration through the power supply pin without using additional lines. The PGA900 operating voltage is from 3.3 to 30 V and it can operate in temperatures from –40°C to 150°C.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
PGA900VQFN (36)6.00 mm x 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

PGA900 Simplified Block Diagram

PGA900 fbd_lds191_pga900.gif