SLAS740A January 2013  – October 2015 RF430F5978

PRODUCTION DATA. 

  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagram
    2. 4.2Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5 Typical Characteristics - Active Mode Supply Currents
    6. 5.6 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    7. 5.7 Typical Characteristics - Low-Power Mode Supply Currents
    8. 5.8 Thermal Resistance Characteristics
    9. 5.9 Digital Inputs
    10. 5.10Digital Outputs
    11. 5.11Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
    12. 5.12Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
    13. 5.13Crystal Oscillator, XT1, Low-Frequency Mode
    14. 5.14Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    15. 5.15Internal Reference, Low-Frequency Oscillator (REFO)
    16. 5.16DCO Frequency
    17. 5.17PMM, Brown-Out Reset (BOR)
    18. 5.18PMM, Core Voltage
    19. 5.19PMM, SVS High Side
    20. 5.20PMM, SVM High Side
    21. 5.21PMM, SVS Low Side
    22. 5.22PMM, SVM Low Side
    23. 5.23Wake-up Times From Low-Power Modes and Reset
    24. 5.24Timer_A
    25. 5.25USCI (UART Mode) Clock Frequency
    26. 5.26USCI (UART Mode)
    27. 5.27USCI (SPI Master Mode) Clock Frequency
    28. 5.28USCI (SPI Master Mode)
    29. 5.29USCI (SPI Slave Mode)
    30. 5.30USCI (I2C Mode)
    31. 5.3112-Bit ADC, Power Supply and Input Range Conditions
    32. 5.3212-Bit ADC, Timing Parameters
    33. 5.3312-Bit ADC, Linearity Parameters
    34. 5.3412-Bit ADC, Temperature Sensor and Built-In VMID
    35. 5.35REF, External Reference
    36. 5.36REF, Built-In Reference
    37. 5.37Comparator B
    38. 5.38Flash Memory
    39. 5.39JTAG and Spy-Bi-Wire Interface
    40. 5.40RF1A CC1101 Radio Parameters
      1. 5.40.1 RF Crystal Oscillator, XT2
      2. 5.40.2 Current Consumption, Reduced-Power Modes
      3. 5.40.3 Current Consumption, Receive Mode
      4. 5.40.4 Current Consumption, Transmit Mode
      5. 5.40.5 Typical TX Current Consumption, 315 MHz
      6. 5.40.6 Typical TX Current Consumption, 433 MHz
      7. 5.40.7 Typical TX Current Consumption, 868 MHz
      8. 5.40.8 Typical TX Current Consumption, 915 MHz
      9. 5.40.9 RF Receive, Overall
      10. 5.40.10RF Receive, 315 MHz
      11. 5.40.11RF Receive, 433 MHz
      12. 5.40.12RF Receive, 868 or 915 MHz
      13. 5.40.13Typical Sensitivity, 315 MHz, Sensitivity-Optimized Setting
      14. 5.40.14Typical Sensitivity, 433 MHz, Sensitivity-Optimized Setting
      15. 5.40.15Typical Sensitivity, 868 MHz, Sensitivity-Optimized Setting
      16. 5.40.16Typical Sensitivity, 915 MHz, Sensitivity-Optimized Setting
      17. 5.40.17RF Transmit
      18. 5.40.18Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
      19. 5.40.19Typical Output Power, 315 MHz
      20. 5.40.20Typical Output Power, 433 MHz
      21. 5.40.21Typical Output Power, 868 MHz
      22. 5.40.22Typical Output Power, 915 MHz
      23. 5.40.23Frequency Synthesizer Characteristics
      24. 5.40.24Typical RSSI_offset Values
    41. 5.413D LF Front-End Parameters
      1. 5.41.1Recommended Operating Conditions
      2. 5.41.2Resonant Circuits - LF Front End
      3. 5.41.3External Antenna Coil - LF Front End
      4. 5.41.4 Resonant Circuit Capacitor - LF Front End
      5. 5.41.5Charge Capacitor - LF Front End
      6. 5.41.6LF Wake Receiver Electrical Characteristics
      7. 5.41.7RSSI - LF Wake Receiver Electrical Characteristics
  6. 6Detailed Description
    1. 6.1 3D LF Wake Receiver and 3D Transponder Interface
      1. 6.1.13D LF Front End
      2. 6.1.2EEPROM
      3. 6.1.3Switch Interface
    2. 6.2 Sub-1-GHz Radio
    3. 6.3 CPU
    4. 6.4 Operating Modes
    5. 6.5 Interrupt Vector Addresses
    6. 6.6 Memory Organization
    7. 6.7 Bootloader (BSL)
    8. 6.8 JTAG Operation
      1. 6.8.1JTAG Standard Interface
      2. 6.8.2Spy-Bi-Wire Interface
    9. 6.9 Flash Memory
    10. 6.10RAM
    11. 6.11Peripherals
      1. 6.11.1 Oscillator and System Clock
      2. 6.11.2 Power-Management Module (PMM)
      3. 6.11.3 Digital I/O
      4. 6.11.4 Port Mapping Controller
      5. 6.11.5 System (SYS) Module
      6. 6.11.6 DMA Controller
      7. 6.11.7 Watchdog Timer (WDT_A)
      8. 6.11.8 CRC16
      9. 6.11.9 Hardware Multiplier
      10. 6.11.10AES128 Accelerator
      11. 6.11.11Universal Serial Communication Interface (USCI)
      12. 6.11.12TA0
      13. 6.11.13TA1
      14. 6.11.14Real-Time Clock (RTC_A)
      15. 6.11.15REF Voltage Reference
      16. 6.11.16Comparator_B
      17. 6.11.17ADC12_A
      18. 6.11.18Embedded Emulation Module (EEM) (S Version)
      19. 6.11.19Peripheral File Map
    12. 6.12Input/Output Schematics
      1. 6.12.1 Port P1, P1.0 to P1.4, Input/Output With Schmitt Trigger
      2. 6.12.2 Port P1, P1.5 to P1.7, Input/Output With Schmitt Trigger
      3. 6.12.3 Port P2, P2.0 to P2.2, Input/Output With Schmitt Trigger
      4. 6.12.4 Port P2, P2.4 and P2.5, Input/Output With Schmitt Trigger
      5. 6.12.5 Port P3, P3.1 to P3.3, P3.5, and P3.7, Input/Output With Schmitt Trigger
      6. 6.12.6 Port P4, P4.0 to P4.2, Input/Output With Schmitt Trigger
      7. 6.12.7 Port P5, P5.0, Input/Output With Schmitt Trigger
      8. 6.12.8 Port P5, P5.1, Input/Output With Schmitt Trigger
      9. 6.12.9 Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      10. 6.12.10Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    13. 6.13Device Descriptor Structures
  7. 7Applications, Implementation, and Layout
    1. 7.1Application Circuit
  8. 8Device and Documentation Support
    1. 8.1Device Support
      1. 8.1.1Development Support
        1. 8.1.1.1Getting Started and Next Steps
      2. 8.1.2Device and Development Tool Nomenclature
    2. 8.2Documentation Support
      1. 8.2.1Related Documentation
    3. 8.3Community Resources
    4. 8.4Trademarks
    5. 8.5Electrostatic Discharge Caution
    6. 8.6Export Control Notice
    7. 8.7Glossary
  9. 9Mechanical, Packaging, and Orderable Information

1 Device Overview

1.1 Features

  • True System-In-Package Based On MSP430™ Microcontroller With Sub-1-GHz Transceiver System-On-Chip (SoC) and Additional 3D LF Wake-up and Transponder Interface
  • Wide Supply Voltage Range:
    3.6 V Down To 1.8 V
  • Ultra-Low Power Consumption
    • CPU Active Mode (AM): 160 µA/MHz
    • Standby Mode (LPM3 Real-Time Clock [RTC] Mode): 2.0 µA
    • Off Mode (LPM4 RAM Retention): 1.0 µA
    • Radio in Receive: 15 mA, 250 kbps, 915 MHz
  • MSP430 System and Peripherals
    • 16-Bit RISC Architecture, Extended Memory, up to 20-MHz System Clock
    • Wake up From Standby Mode in Less Than 6 µs
    • Flexible Power-Management System With SVS and Brownout
    • Unified Clock System With FLL
    • 16-Bit Timer TA0, Timer_A With Five Capture/Compare Registers
    • 16-Bit Timer TA1, Timer_A With Three Capture/Compare Registers
    • Hardware RTC
    • Two Universal Serial Communication Interfaces (USCIs)
      • USCI_A0 Supports UART, IrDA, SPI
      • USCI_B0 Supports I2C, SPI
    • 12-Bit Analog-to-Digital Converter (ADC) With Internal Reference, Sample-and-Hold, and Autoscan Features
    • Comparator
    • 128-Bit AES Security Encryption and Decryption Coprocessor
    • 32-Bit Hardware Multiplier
    • 3-Channel Internal DMA
    • Serial Onboard Programming, No External Programming Voltage Needed
    • Embedded Emulation Module (EEM)
  • High-Performance Sub-1-GHz Radio Frequency (RF) Transceiver Core
    • Same as in CC1101
    • Wide Supply Voltage Range: 2 V to 3.6 V
    • Frequency Bands: 300 MHz to 348 MHz, 389 MHz to 464 MHz, and 779 MHz to 928 MHz
    • Programmable Data Rate From 0.6 kBaud to 500 kBaud
    • High Sensitivity (–117 dBm at 0.6 kBaud, –111 dBm at 1.2 kBaud, 315 MHz, 1% Packet Error Rate)
    • Excellent Receiver Selectivity and Blocking Performance
    • Programmable Output Power up to +12 dBm for All Supported Frequencies
    • 2-FSK, 2-GFSK, and MSK Supported as Well as OOK and Flexible ASK Shaping
    • Flexible Support for Packet-Oriented Systems: On-Chip Support for Sync Word Detection, Address Check, Flexible Packet Length, and Automatic CRC Handling
    • Support for Automatic Clear Channel Assessment (CCA) Before Transmitting (for Listen-Before-Talk Systems)
    • Digital RSSI Output
    • Suited for Systems Targeting Compliance With EN 300 220 (Europe) and FCC CFR Part 15 (US)
    • Suited for Systems Targeting Compliance With Wireless M-Bus Standard EN 13757-4:2005
    • Support for Asynchronous and Synchronous Serial Receive and Transmit Mode for Backward Compatibility With Existing Radio Communication Protocols
  • High-Performance Low-Frequency (LF) Interface
    • 3D Wake-up Receiver
      • Low Standby Current Consumption: 4.4 µA
      • Regular Sensitivity Mode:
        3.7 mVpp → Approximate 3-m Wake Range
      • High Sensitivity Mode:
        0.5 mVpp → Approximate 6-m Wake Range
      • Low Sensitivity Variation
      • Digital RSSI, 72 dB, 8-Bit Logarithmic
      • Two Independent Wake Patterns, 0-Bit to 24-Bit Length
      • Dedicated Sensitivity Levels for Both Wake Patterns
      • Integrated LF Bit Stream Data Decoding and Digital Data Output
    • AES-128 Hardware Encryption Coprocessor
    • Resonant Frequency: 134.2 kHz
      • Embedded Resonant Trimming for All Three Resonant Circuits
    • 3D Transponder Interface
      • Transponder Read Range up to 4 in (10 cm), Power Received From LF RF Field
      • Half-Duplex (HDX) Communication Protocol
      • Selectable Challenge/Response Length: 32/32, 64/64, or 96/64 Bit
      • Mutual Authentication For All Commands With 32-Bit Reader Signature
      • Burst Read Mode
      • Anticollision Encryption
    • EEPROM Memory Size of 2048 Bytes
      • Available User EEPROM is 1776 Bytes
      • Encryption Keys 4 × 128 Bits
      • Configurable Page Types for Selective Access Grant
      • All Pages Lockable (No Reprogramming Possible)
    • Switch Interface With up to Eight Inputs

1.2 Applications

  • Wireless Analog Sensor Systems
  • Wireless Digital Sensor Systems
  • Access Control
  • Asset Tracking
  • Smart Grid Wireless Networks

1.3 Description

The TI RF430F5978 system-in-package adds a 3D low-frequency (LF) wake-up and transponder interface to the CC430 ultra-low-power microcontroller system-on-chip (SoC) with integrated sub-1-GHz RF transceiver. This architecture allows activation and deactivation of the device in a dedicated and well-defined area "on-demand" to achieve extended battery life for the whole system. The embedded LF transponder interface is always functional even without battery supply and offers the highest level of security through its 128-bit AES encryption for challenge/response and mutual authentication. The embedded LF transponder interface also adds 2KB of programmable EEPROM memory to the system.

The CC430 ultra-low-power microcontroller system-on-chip (SoC) combines the CC1101 sub-1-GHz RF transceiver with the powerful MSP430 16-bit RISC CPU. Sixteen-bit registers and constant generators contribute to maximum code efficiency. The RF430F5978 device features the MSP430 CPUXV2, 32KB of in-system programmable flash memory, 4KB of RAM, two 16-bit timers, a high-performance 12-bit ADC with six external inputs plus internal temperature and battery sensors, a comparator, two USCIs, a 128-bit AES security accelerator, a hardware multiplier, DMA, and an RTC module with alarm capabilities.

The RF430F5978 provides a tight integration between the microcontroller core, its peripherals, software, and the integrated sub-1-GHz RF transceiver and 3D LF transceiver for wake-up and transponder interface, making these solutions easy to use while improving performance.

For complete module descriptions, see the RF430 Family User's Guide (SLAU378).

Device Information(1)

PART NUMBERPACKAGEBODY SIZE(2)
RF430F5978IRGC VQFN (64)9 mm × 9 mm
(1) For the most current part, package, and ordering information, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.
(2) The size shown here is an approximation. For the package dimensions with tolerances, see the Mechanical Data in Section 9.

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram.

RF430F5978 bd_f59xx_slas740.gif Figure 1-1 Functional Block Diagram