SLAS740A January   2013  – October 2015 RF430F5978

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics - Active Mode Supply Currents
    6. 5.6  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Typical Characteristics - Low-Power Mode Supply Currents
    8. 5.8  Thermal Resistance Characteristics
    9. 5.9  Digital Inputs
    10. 5.10 Digital Outputs
    11. 5.11 Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
    12. 5.12 Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
    13. 5.13 Crystal Oscillator, XT1, Low-Frequency Mode
    14. 5.14 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    15. 5.15 Internal Reference, Low-Frequency Oscillator (REFO)
    16. 5.16 DCO Frequency
    17. 5.17 PMM, Brown-Out Reset (BOR)
    18. 5.18 PMM, Core Voltage
    19. 5.19 PMM, SVS High Side
    20. 5.20 PMM, SVM High Side
    21. 5.21 PMM, SVS Low Side
    22. 5.22 PMM, SVM Low Side
    23. 5.23 Wake-up Times From Low-Power Modes and Reset
    24. 5.24 Timer_A
    25. 5.25 USCI (UART Mode) Clock Frequency
    26. 5.26 USCI (UART Mode)
    27. 5.27 USCI (SPI Master Mode) Clock Frequency
    28. 5.28 USCI (SPI Master Mode)
    29. 5.29 USCI (SPI Slave Mode)
    30. 5.30 USCI (I2C Mode)
    31. 5.31 12-Bit ADC, Power Supply and Input Range Conditions
    32. 5.32 12-Bit ADC, Timing Parameters
    33. 5.33 12-Bit ADC, Linearity Parameters
    34. 5.34 12-Bit ADC, Temperature Sensor and Built-In VMID
    35. 5.35 REF, External Reference
    36. 5.36 REF, Built-In Reference
    37. 5.37 Comparator B
    38. 5.38 Flash Memory
    39. 5.39 JTAG and Spy-Bi-Wire Interface
    40. 5.40 RF1A CC1101 Radio Parameters
      1. 5.40.1  RF Crystal Oscillator, XT2
      2. 5.40.2  Current Consumption, Reduced-Power Modes
      3. 5.40.3  Current Consumption, Receive Mode
      4. 5.40.4  Current Consumption, Transmit Mode
      5. 5.40.5  Typical TX Current Consumption, 315 MHz
      6. 5.40.6  Typical TX Current Consumption, 433 MHz
      7. 5.40.7  Typical TX Current Consumption, 868 MHz
      8. 5.40.8  Typical TX Current Consumption, 915 MHz
      9. 5.40.9  RF Receive, Overall
      10. 5.40.10 RF Receive, 315 MHz
      11. 5.40.11 RF Receive, 433 MHz
      12. 5.40.12 RF Receive, 868 or 915 MHz
      13. 5.40.13 Typical Sensitivity, 315 MHz, Sensitivity-Optimized Setting
      14. 5.40.14 Typical Sensitivity, 433 MHz, Sensitivity-Optimized Setting
      15. 5.40.15 Typical Sensitivity, 868 MHz, Sensitivity-Optimized Setting
      16. 5.40.16 Typical Sensitivity, 915 MHz, Sensitivity-Optimized Setting
      17. 5.40.17 RF Transmit
      18. 5.40.18 Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
      19. 5.40.19 Typical Output Power, 315 MHz
      20. 5.40.20 Typical Output Power, 433 MHz
      21. 5.40.21 Typical Output Power, 868 MHz
      22. 5.40.22 Typical Output Power, 915 MHz
      23. 5.40.23 Frequency Synthesizer Characteristics
      24. 5.40.24 Typical RSSI_offset Values
    41. 5.41 3D LF Front-End Parameters
      1. 5.41.1 Recommended Operating Conditions
      2. 5.41.2 Resonant Circuits - LF Front End
      3. 5.41.3 External Antenna Coil - LF Front End
      4. 5.41.4 Resonant Circuit Capacitor - LF Front End
      5. 5.41.5 Charge Capacitor - LF Front End
      6. 5.41.6 LF Wake Receiver Electrical Characteristics
      7. 5.41.7 RSSI - LF Wake Receiver Electrical Characteristics
  6. 6Detailed Description
    1. 6.1  3D LF Wake Receiver and 3D Transponder Interface
      1. 6.1.1 3D LF Front End
      2. 6.1.2 EEPROM
      3. 6.1.3 Switch Interface
    2. 6.2  Sub-1-GHz Radio
    3. 6.3  CPU
    4. 6.4  Operating Modes
    5. 6.5  Interrupt Vector Addresses
    6. 6.6  Memory Organization
    7. 6.7  Bootloader (BSL)
    8. 6.8  JTAG Operation
      1. 6.8.1 JTAG Standard Interface
      2. 6.8.2 Spy-Bi-Wire Interface
    9. 6.9  Flash Memory
    10. 6.10 RAM
    11. 6.11 Peripherals
      1. 6.11.1  Oscillator and System Clock
      2. 6.11.2  Power-Management Module (PMM)
      3. 6.11.3  Digital I/O
      4. 6.11.4  Port Mapping Controller
      5. 6.11.5  System (SYS) Module
      6. 6.11.6  DMA Controller
      7. 6.11.7  Watchdog Timer (WDT_A)
      8. 6.11.8  CRC16
      9. 6.11.9  Hardware Multiplier
      10. 6.11.10 AES128 Accelerator
      11. 6.11.11 Universal Serial Communication Interface (USCI)
      12. 6.11.12 TA0
      13. 6.11.13 TA1
      14. 6.11.14 Real-Time Clock (RTC_A)
      15. 6.11.15 REF Voltage Reference
      16. 6.11.16 Comparator_B
      17. 6.11.17 ADC12_A
      18. 6.11.18 Embedded Emulation Module (EEM) (S Version)
      19. 6.11.19 Peripheral File Map
    12. 6.12 Input/Output Schematics
      1. 6.12.1  Port P1, P1.0 to P1.4, Input/Output With Schmitt Trigger
      2. 6.12.2  Port P1, P1.5 to P1.7, Input/Output With Schmitt Trigger
      3. 6.12.3  Port P2, P2.0 to P2.2, Input/Output With Schmitt Trigger
      4. 6.12.4  Port P2, P2.4 and P2.5, Input/Output With Schmitt Trigger
      5. 6.12.5  Port P3, P3.1 to P3.3, P3.5, and P3.7, Input/Output With Schmitt Trigger
      6. 6.12.6  Port P4, P4.0 to P4.2, Input/Output With Schmitt Trigger
      7. 6.12.7  Port P5, P5.0, Input/Output With Schmitt Trigger
      8. 6.12.8  Port P5, P5.1, Input/Output With Schmitt Trigger
      9. 6.12.9  Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      10. 6.12.10 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    13. 6.13 Device Descriptor Structures
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Circuit
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Getting Started and Next Steps
      2. 8.1.2 Device and Development Tool Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Community Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Export Control Notice
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Detailed Description

6.1 3D LF Wake Receiver and 3D Transponder Interface

Figure 6-1 shows the LF interface block diagram.

RF430F5978 bd_lf_interface_RF430F59xx_slas740.gif Figure 6-1 LF Interface Block Diagram

The LF front end provides a SPI that is used for the communication with the CPU core. Data access, configuration, and status queries to the MSP430 core are executed with predefined commands over this interface, which is internally connected to IO ports (see Table 6-1).

Table 6-1 Intermodule Connections for RF430F59xx

MICROCONTROLLER PORT LF FRONT-END MODULE PORT
P3.1 Input SPI_SOMI
P3.2 Output SPI_SIMO
P3.3 Output SPI_CLK
P3.5 Input CLK_OUT
P4.1 Input EOB
P4.2 Input SPI_BUSY

6.1.1 3D LF Front End

The 3D LF front end provides two basic operation modes: transponder mode and wake receiver mode. The LF front end provides an external trigger to wake up the microcontroller on LF reception. Data received by the LF interface and status of the device can be read through SPI communication. Features of the LF front end include:

  • Resonant frequency: 134.2 kHz
    • Embedded resonant trimming for all three resonant circuits
  • Quality factor range: 10 to 60
  • Antenna Inductance 2.66 mH, 4.5 mH, or 7.6 mH
  • AES-128 hardware-encryption coprocessor
  • 3D wake receiver
    • Fixed downlink start pattern S10
    • Downlink data rate up to 4 kBps with bit-length coding
    • Two independent wake patterns WP A or WP B with 0-, 4-, 8-, 12-, 16-, 20-, or 24-bit length
      • Dedicated sensitivity levels for both WP
    • Digital RSSI 72 dB, 8-bit logarithmic
      • Accuracy ±8% in near distance (<16 mVpp)
      • Accuracy ±20% in far distance (>16 mVpp)
  • 3D RFID transponder interface
    • Batteryless operation
    • Fixed downlink start pattern S01
    • Transponder read range up to 4 inches (10 cm)
    • Half-duplex communication protocol
      • Adaptive downlink data rate: up to 4 kbaud with ASK, bit-length coding
      • Uplink data rate: up to 8 kbaud with FSK
    • Selectable challenge/response length of 32/32, 64/64, or 96/64 bit
    • Mutual authentication for all commands with 32-bit reader signature
    • Selective addressing mode, 8 bit
    • Burst read mode
    • Anticollision encryption

6.1.2 EEPROM

The EEPROM can be accessed by SPI commands. Features of the EEPROM include:

  • Total memory size: 2048 Bytes
  • User memory size: 1776 Bytes
    • User memory has up to 4 banks
    • User memory is organized in 64 pages per bank of 8 bytes each
  • EEPROM has one system memory bank organized in 64 pages of 4 bytes each.
    • System memory is organized in 64 pages of 4 bytes each
    • System memory is used for special information (configuration, four 128-bit encryption keys, counter values)
  • The memory pages are configurable and provide different access modes
    • General-purpose memory (general read, program, and lock)
    • System only data (mutual only access)
    • Microcontroller only data (no access over LF interface)
    • Secured data (mutual program and lock, general read)
  • All pages can be locked separately (no reprogramming possible)

Table 6-2 summarizes the EEPROM organization.

6.1.3 Switch Interface

The switch interface provides eight inputs. Features of the switch interface include:

  • Internal pullups to minimize external components
  • Embedded stuck button handling
  • Embedded debouncing for each switch debounce time: 10, 20, 40, or 80 ms

Table 6-2 LF Front End EEPROM Memory Map

EEPROM (MEM)
BANK BYTE PAGE
7 6 5 4 3 2 1 0
0 User Data 0
⋮ ⋮
User Data 7
⋮ ⋮
User Data 63
1 User Data 0
⋮ ⋮
User Data 7
⋮ ⋮
User Data 63
2 User Data 0
⋮ ⋮
User Data 7
⋮ ⋮
User Data 63
3 User Data 0
⋮ ⋮
User Data 7
⋮ ⋮
User Data 29
7 Configuration Data Configuration Data 1 0
3 2
5 4
7 6
9 8
11 10
13 12
15 14
Encryption Keys Encryption Keys 17 16
19 18
21 20
23 22
25 24
27 26
29 28
31 30

6.2 Sub-1-GHz Radio

The sub-1-GHz radio module is based on the industry-leading CC1101 and requires very few external components. Figure 6-2 shows a high-level block diagram of the implemented radio.

RF430F5978 bd_radio_slas740.gif Figure 6-2 Sub-1-GHz Radio Block Diagram

The radio features a low intermediate frequency (IF) receiver. The received RF signal is amplified by a low-noise amplifier (LNA) and down converted in quadrature to the IF. At the IF, the I/Q signals are digitized. Automatic gain control (AGC), fine channel filtering, and demodulation bit and packet synchronization are performed digitally.

The transmitter is based on direct synthesis of the RF frequency. The frequency synthesizer includes a completely on-chip LC VCO and a 90-degree phase shifter for generating the I and Q LO signals to the down-conversion mixers in receive mode.

The 26-MHz crystal oscillator generates the reference frequency for the synthesizer and the clocks for the ADC and the digital peripherals.

A memory-mapped register interface is used for data access, configuration, and status request by the CPU.

The digital baseband includes support for channel configuration, packet handling, and data buffering.

For complete module descriptions, see the RF430F5978 User's Guide (SLAU378).

6.3 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data.

6.4 Operating Modes

The device has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following operating modes can be configured by software:

  • Active mode (AM)
    • All clocks are active
  • Low-power mode 0 (LPM0)
    • CPU is disabled
    • ACLK and SMCLK remain active, MCLK is disabled
    • FLL loop control remains active
  • Low-power mode 1 (LPM1)
    • CPU is disabled
    • FLL loop control is disabled
    • ACLK and SMCLK remain active, MCLK is disabled
  • Low-power mode 2 (LPM2)
    • CPU is disabled
    • MCLK and FLL loop control and DCOCLK are disabled
    • DC generator of the DCO remains enabled
    • ACLK remains active
  • Low-power mode 3 (LPM3)
    • CPU is disabled
    • MCLK, FLL loop control, and DCOCLK are disabled
    • DC generator of the DCO is disabled
    • ACLK remains active
  • Low-power mode 4 (LPM4)
    • CPU is disabled
    • ACLK is disabled
    • MCLK, FLL loop control, and DCOCLK are disabled
    • DC generator of the DCO is disabled
    • Crystal oscillator is stopped
    • Complete data retention

6.5 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 6-3 Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
System Reset
Power-Up
External Reset
Watchdog Time-out, Password Violation
Flash Memory Password Violation		 WDTIFG, KEYV (SYSRSTIV)(2) (1) Reset 0FFFEh 63, highest
System NMI
PMM
Vacant Memory Access
JTAG Mailbox		 SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV)(2) (3) (Non)maskable 0FFFCh 62
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation		 NMIIFG, OFIFG, ACCVIFG (SYSUNIV)(2) (3) (Non)maskable 0FFFAh 61
Comparator_B Comparator_B Interrupt Flags (CBIV)(2) Maskable 0FFF8h 60
Watchdog Interval Timer Mode WDTIFG Maskable 0FFF6h 59
USCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)(2) Maskable 0FFF4h 58
USCI_B0 Receive or Transmit UCB0RXIFG, UCB0TXIFG, I2C Status Interrupt Flags (UCB0IV)(2) Maskable 0FFF2h 57
ADC12_A ADC12IFG0 ... ADC12IFG15 (ADC12IV)(2) Maskable 0FFF0h 56
TA0 TA0CCR0 CCIFG0 Maskable 0FFEEh 55
TA0 TA0CCR1 CCIFG1 ... TA0CCR4 CCIFG4,
TA0IFG (TA0IV)(2)		 Maskable 0FFECh 54
RF1A CC1101-based Radio Radio Interface Interrupt Flags (RF1AIFIV)
Radio Core Interrupt Flags (RF1AIV)		 Maskable 0FFEAh 53
DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(2) Maskable 0FFE8h 52
TA1 TA1CCR0 CCIFG0 Maskable 0FFE6h 51
TA1 TA1CCR1 CCIFG1 ... TA1CCR2 CCIFG2,
TA1IFG (TA1IV)(2)		 Maskable 0FFE4h 50
I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)(2) Maskable 0FFE2h 49
I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)(2) Maskable 0FFE0h 48
Reserved Reserved(4) 0FFDEh 47
RTC_A RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV)(2) Maskable 0FFDCh 46
AES AESRDYIFG Maskable 0FFDAh 45
Reserved Reserved(4) 0FFD8h 44
⋮ ⋮
0FF80h 0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within peripheral space.
(2) Multiple source flags
(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot disable it.
(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, TI recommends reserving these locations.

6.6 Memory Organization

Table 6-4 summarizes the memory organization of the device.

Table 6-4 Memory Organization

RF430F5978(1)
Main Memory (flash) Total Size 32KB
Main: Interrupt vector 00FFFFh to 00FF80h
Main: code memory Bank 0 32KB
00FFFFh to 008000h
RAM Total Size 4KB
Sect 1 2KB
002BFFh to 002400h
Sect 0 2KB
0023FFh to 001C00h
Device descriptor 128 B
001AFFh to 001A80h
128 B
001A7Fh to 001A00h
Information memory (flash) Info A 128 B
0019FFh to 001980h
Info B 128 B
00197Fh to 001900h
Info C 128 B
0018FFh to 001880h
Info D 128 B
00187Fh to 001800h
Bootloader (BSL) memory (flash) BSL 3 512 B
0017FFh to 001600h
BSL 2 512 B
0015FFh to 001400h
BSL 1 512 B
0013FFh to 001200h
BSL 0 512 B
0011FFh to 001000h
Peripherals 4KB
000FFFh to 0h
(1) All memory regions not specified here are vacant memory, and any access to them causes a Vacant Memory Interrupt.

6.7 Bootloader (BSL)

The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the device memory through the BSL is protected by an user-defined password. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of the features of the BSL and its implementation, see the MSP430 Programming With the Bootloader User's Guide (SLAU319). Table 6-5 lists the BSL in requirements.

Table 6-5 UART BSL Pin Requirements and Functions

DEVICE SIGNAL BSL FUNCTION
RST/NMI/SBWTDIO Entry sequence signal
TEST/SBWTCK Entry sequence signal
P1.6 Data transmit
P1.5 Data receive
VCC Power supply
VSS Ground supply

6.8 JTAG Operation

6.8.1 JTAG Standard Interface

The RF430F5978 supports the standard JTAG interface, which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/Os. The TEST/SBWTCK pin enables the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO pin is required to interface with MSP430 development tools and device programmers. Table 6-6 lists the JTAG pin requirements. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320).

Table 6-6 JTAG Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION
PJ.3/TCK IN JTAG clock input
PJ.2/TMS IN JTAG state control
PJ.1/TDI/TCLK IN JTAG data input, TCLK input
PJ.0/TDO OUT JTAG data output
TEST/SBWTCK IN Enable JTAG pins
RST/NMI/SBWTDIO IN External reset
VCC Power supply
VSS Ground supply

6.8.2 Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the RF430F5978 supports the two-wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 6-7 lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320).

Table 6-7 Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION
TEST/SBWTCK IN Spy-Bi-Wire clock input
RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input and output
VCC Power supply
VSS Ground supply

6.9 Flash Memory

The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash memory include:

  • Flash memory has n segments of main memory and four segments of information memory (Info A to Info D) of 128 bytes each. Each segment in main memory is 512 bytes in size.
  • Segments 0 to n may be erased in one step, or each segment may be individually erased.
  • Segments Info A to Info D can be erased individually, or as a group with the main memory segments. Segments Info A to Info D are also called information memory.
  • Segment A can be locked separately.

6.10 RAM

The RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however, all data are lost. Features of the RAM include:

  • RAM has n sectors of 2KB each.
  • Each sector 0 to n can be complete disabled; however, data retention is lost.
  • Each sector 0 to n automatically enters low-power retention mode when possible.

6.11 Peripherals

Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be handled using all instructions. For complete module descriptions, see the RF430F5978 User's Guide (SLAU378).

6.11.1 Oscillator and System Clock

The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator. The UCS module is designed to meet the requirements of both low system cost and low power consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turnon clock source and stabilizes in less than 5 µs. The UCS module provides the following clock signals:

  • Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, the internal low-frequency oscillator (VLO), or the trimmed low-frequency oscillator (REFO).
  • Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made available to ACLK.
  • Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by same sources that are available to ACLK.
  • ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

6.11.2 Power-Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor (SVS) and supply voltage monitor (SVM) circuitry, as well as brownout protection. The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.

6.11.3 Digital I/O

Five I/O ports are implemented: ports P1 through P3 are 8 bit, P4 is 1 bit, and P5 is 2 bit.

  • All individual I/O bits are independently programmable.
  • Any combination of input, output, and interrupt conditions is possible.
  • Programmable pullup or pulldown on all ports.
  • Programmable drive strength on all ports.
  • Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
  • Read and write access to port-control registers is supported by all instructions.
  • Ports can be accessed byte-wise (P1 through P3) or word-wise in pairs (PA and PB).

6.11.4 Port Mapping Controller

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port pins of ports P1 through P3. Table 6-8 lists the available port mapping assignments, and Table 6-9 lists the default assignments.

Table 6-8 Port Mapping Mnemonics and Functions

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION
(PxDIR.y = 0)		 OUTPUT PIN FUNCTION
(PxDIR.y = 1)
0 PM_NONE None DVSS
1(1) PM_CBOUT0 – Comparator_B output (on TA0 clock input)
PM_TA0CLK TA0 clock input –
2(1) PM_CBOUT1 – Comparator_B output (on TA1 clock input)
PM_TA1CLK TA1 clock input –
3 PM_ACLK None ACLK output
4 PM_MCLK None MCLK output
5 PM_SMCLK None SMCLK output
6 PM_RTCCLK None RTCCLK output
7(1) PM_ADC12CLK – ADC12CLK output
PM_DMAE0 DMA external trigger input –
8 PM_SVMOUT None SVM output
9 PM_TA0CCR0A TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0
10 PM_TA0CCR1A TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1
11 PM_TA0CCR2A TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2
12 PM_TA0CCR3A TA0 CCR3 capture input CCI3A TA0 CCR3 compare output Out3
13 PM_TA0CCR4A TA0 CCR4 capture input CCI4A TA0 CCR4 compare output Out4
14 PM_TA1CCR0A TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0
15 PM_TA1CCR1A TA1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1
16 PM_TA1CCR2A TA1 CCR2 capture input CCI2A TA1 CCR2 compare output Out2
17(2) PM_UCA0RXD USCI_A0 UART RXD (direction controlled by USCI – input)
PM_UCA0SOMI USCI_A0 SPI slave out/master in (direction controlled by USCI)
18(2) PM_UCA0TXD USCI_A0 UART TXD (direction controlled by USCI – output)
PM_UCA0SIMO USCI_A0 SPI slave in/master out (direction controlled by USCI)
19(3) PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)
20(4) PM_UCB0SOMI USCI_B0 SPI slave out/master in (direction controlled by USCI)
PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)
21(4) PM_UCB0SIMO USCI_B0 SPI slave in/master out (direction controlled by USCI)
PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)
22(5) PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI)
PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
23 PM_RFGDO0 Radio GDO0 (direction controlled by radio)
24 PM_RFGDO1 Radio GDO1 (direction controlled by radio)
25 PM_RFGDO2 Radio GDO2 (direction controlled by Radio)
26 Reserved None DVSS
27 Reserved None DVSS
28 Reserved None DVSS
29 Reserved None DVSS
30 Reserved None DVSS
31 (0FFh)(6) PM_ANALOG Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals.
(1) Input or output function is selected by the corresponding setting in the port direction register PxDIR.
(2) UART or SPI functionality is determined by the selected USCI mode.
(3) UCA0CLK function takes precedence over UCB0STE function. If the mapped pin is required as UCA0CLK input or output, USCI_B0 is forced to 3-wire SPI mode even if 4-wire mode is selected.
(4) SPI or I2C functionality is determined by the selected USCI mode. If I2C functionality is selected, the output of the mapped pin drives only the logical 0 to VSS level.
(5) UCB0CLK function takes precedence over UCA0STE function. If the mapped pin is required as UCB0CLK input or output, USCI_A0 is forced to 3-wire SPI mode even if 4-wire mode is selected.
(6) The value of the PM_ANALOG mnemonic is FFh. The port mapping registers are 5 bits wide, and the upper bits are ignored, which results in a read value of 31.

Table 6-9 Default Mapping

PIN PxMAPy MNEMONIC INPUT PIN FUNCTION (PxDIR.y = 0) OUTPUT PIN FUNCTION (PxDIR.y = 1)
P1.0/P1MAP0 PM_RFGDO0 None Radio GDO0
P1.1/P1MAP1 PM_RFGDO2 None Radio GDO2
P1.2/P1MAP2 PM_UCB0SOMI/PM_UCB0SCL USCI_B0 SPI slave out/master in (direction controlled by USCI)
USCI_B0 I2C clock (open drain and direction controlled by USCI)
P1.3/P1MAP3 PM_UCB0SIMO/PM_UCB0SDA USCI_B0 SPI slave in/master out (direction controlled by USCI)
USCI_B0 I2C data (open drain and direction controlled by USCI)
P1.4/P1MAP4 PM_UCB0CLK/PM_UCA0STE USCI_B0 clock input/output (direction controlled by USCI)
USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
P1.5/P1MAP5 PM_UCA0RXD/PM_UCA0SOMI USCI_A0 UART RXD (direction controlled by USCI – input)
USCI_A0 SPI slave out/master in (direction controlled by USCI)
P1.6/P1MAP6 PM_UCA0TXD/PM_UCA0SIMO USCI_A0 UART TXD (direction controlled by USCI – output)
USCI_A0 SPI slave in/master out (direction controlled by USCI)
P1.7/P1MAP7 PM_UCA0CLK/PM_UCB0STE USCI_A0 clock input/output (direction controlled by USCI)
USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)
P2.0/P2MAP0 PM_CBOUT1/PM_TA1CLK TA1 clock input Comparator_B output
P2.1/P2MAP1 PM_TA1CCR0A TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0
P2.2/P2MAP2 PM_TA1CCR1A TA1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1
P2.3/P2MAP3 PM_TA1CCR2A TA1 CCR2 capture input CCI2A TA1 CCR2 compare output Out2
P2.4/P2MAP4 PM_RTCCLK None RTCCLK output
P2.5/P2MAP5 PM_SVMOUT None SVM output
P2.6/P2MAP6 PM_ACLK None ACLK output
P2.7/P2MAP7 PM_ADC12CLK/PM_DMAE0 DMA external trigger input ADC12CLK output
P3.0/P3MAP0 PM_CBOUT0/PM_TA0CLK TA0 clock input Comparator_B output
P3.1/P3MAP1 PM_TA0CCR0A TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0
P3.2/P3MAP2 PM_TA0CCR1A TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1
P3.3/P3MAP3 PM_TA0CCR2A TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2
P3.4/P3MAP4 PM_TA0CCR3A TA0 CCR3 capture input CCI3A TA0 CCR3 compare output Out3
P3.5/P3MAP5 PM_TA0CCR4A TA0 CCR4 capture input CCI4A TA0 CCR4 compare output Out4
P3.6/P3MAP6 PM_RFGDO1 None Radio GDO1
P3.7/P3MAP7 PM_SMCLK None SMCLK output

6.11.5 System (SYS) Module

The SYS module handles many of the system functions within the device. These functions include power-on reset (POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector generators, bootloader entry mechanisms, and configuration management (device descriptors). The SYS module also includes a data exchange mechanism through JTAG called a JTAG mailbox that can be used in the application. Table 6-10 lists the interrupt vector registers supported by the SYS module.

Table 6-10 System Module Interrupt Vector Registers

INTERRUPT VECTOR REGISTER ADDRESS INTERRUPT EVENT VALUE PRIORITY
SYSRSTIV, System Reset 019Eh No interrupt pending 00h
Brownout (BOR) 02h Highest
RST/NMI (POR) 04h
DoBOR (BOR) 06h
Reserved 08h
Security violation (BOR) 0Ah
SVSL (POR) 0Ch
SVSH (POR) 0Eh
SVML_OVP (POR) 10h
SVMH_OVP (POR) 12h
DoPOR (POR) 14h
WDT time-out (PUC) 16h
WDT password violation (PUC) 18h
KEYV flash password violation (PUC) 1Ah
Reserved 1Ch
Peripheral area fetch (PUC) 1Eh
PMM password violation (PUC) 20h
Reserved 22h to 3Eh Lowest
SYSSNIV, System NMI 019Ch No interrupt pending 00h
SVMLIFG 02h Highest
SVMHIFG 04h
DLYLIFG 06h
DLYHIFG 08h
VMAIFG 0Ah
JMBINIFG 0Ch
JMBOUTIFG 0Eh
VLRLIFG 10h
VLRHIFG 12h
Reserved 14h to 1Eh Lowest
SYSUNIV, User NMI 019Ah No interrupt pending 00h
NMIIFG 02h Highest
OFIFG 04h
ACCVIFG 06h
Reserved 08h to 1Eh Lowest

6.11.6 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral. Table 6-11 lists the available DMA trigger assignments.

Table 6-11 DMA Trigger Assignments(1)

TRIGGER CHANNEL
0 1 2
0 DMAREQ DMAREQ DMAREQ
1 TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG
2 TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG
3 TA1CCR0 CCIFG TA1CCR0 CCIFG TA1CCR0 CCIFG
4 TA1CCR2 CCIFG TA1CCR2 CCIFG TA1CCR2 CCIFG
5 Reserved Reserved Reserved
6 Reserved Reserved Reserved
7 Reserved Reserved Reserved
8 Reserved Reserved Reserved
9 Reserved Reserved Reserved
10 Reserved Reserved Reserved
11 Reserved Reserved Reserved
12 Reserved Reserved Reserved
13 Reserved Reserved Reserved
14 Reserved Reserved Reserved
15 Reserved Reserved Reserved
16 UCA0RXIFG UCA0RXIFG UCA0RXIFG
17 UCA0TXIFG UCA0TXIFG UCA0TXIFG
18 UCB0RXIFG UCB0RXIFG UCB0RXIFG
19 UCB0TXIFG UCB0TXIFG UCB0TXIFG
20 Reserved Reserved Reserved
21 Reserved Reserved Reserved
22 Reserved Reserved Reserved
23 Reserved Reserved Reserved
24 ADC12IFGx ADC12IFGx ADC12IFGx
25 Reserved Reserved Reserved
26 Reserved Reserved Reserved
27 Reserved Reserved Reserved
28 Reserved Reserved Reserved
29 MPY ready MPY ready MPY ready
30 DMA2IFG DMA0IFG DMA1IFG
31 DMAE0 DMAE0 DMAE0
(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not cause any DMA trigger event when selected.

6.11.7 Watchdog Timer (WDT_A)

The primary function of the watchdog timer is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the timer can be configured as an interval timer and can generate interrupts at selected time intervals.

6.11.8 CRC16

The CRC16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

6.11.9 Hardware Multiplier

The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed and unsigned multiply-and-accumulate operations.

6.11.10 AES128 Accelerator

The AES accelerator module performs encryption and decryption of 128-bit data with 128-bit keys according to the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware.

6.11.11 Universal Serial Communication Interface (USCI)

The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baud-rate detection, and IrDA.

The USCI_An module provides support for SPI (3- or 4-pin), UART, enhanced UART, and IrDA.

The USCI_Bn module provides support for SPI (3- or 4-pin) and I2C.

A USCI_A0 and USCI_B0 module are implemented.

6.11.12 TA0

TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple capture/compares, PWM outputs, and interval timing. TA0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers (see Table 6-12).

Table 6-12 TA0 Signal Connections

DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
PM_TA0CLK TACLK Timer NA
ACLK (internal) ACLK
SMCLK (internal) SMCLK
RFCLK/192(1) INCLK
PM_TA0CCR0A CCI0A CCR0 TA0 PM_TA0CCR0A
DVSS CCI0B
DVSS GND
DVCC VCC
PM_TA0CCR1A CCI1A CCR1 TA1 PM_TA0CCR1A
CBOUT (internal) CCI1B ADC12 (internal)
ADC12SHSx = {1}
DVSS GND
DVCC VCC
PM_TA0CCR2A CCI2A CCR2 TA2 PM_TA0CCR2A
ACLK (internal) CCI2B
DVSS GND
DVCC VCC
PM_TA0CCR3A CCI3A CCR3 TA3 PM_TA0CCR3A
GDO1 from Radio (internal) CCI3B
DVSS GND
DVCC VCC
PM_TA0CCR4A CCI4A CCR4 TA4 PM_TA0CCR4A
GDO2 from Radio (internal) CCI4B
DVSS GND
DVCC VCC
(1) If a different RFCLK divider setting is selected for a radio GDO output, this divider setting is also used for the Timer_A INCLK.

6.11.13 TA1

TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support multiple capture/compares, PWM outputs, and interval timing. TA1 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers (see Table 6-13).

Table 6-13 TA1 Signal Connections

DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
PZ
PM_TA1CLK TACLK Timer NA
ACLK (internal) ACLK
SMCLK (internal) SMCLK
RFCLK/192(1) INCLK
PM_TA1CCR0A CCI0A CCR0 TA0 PM_TA1CCR0A
RF Async. Output (internal) CCI0B RF Async. Input (internal)
DVSS GND
DVCC VCC
PM_TA1CCR1A CCI1A CCR1 TA1 PM_TA1CCR1A
CBOUT (internal) CCI1B
DVSS GND
DVCC VCC
PM_TA1CCR2A CCI2A CCR2 TA2 PM_TA1CCR2A
ACLK (internal) CCI2B
DVSS GND
DVCC VCC
(1) If a different RFCLK divider setting is selected for a radio GDO output, this divider setting is also used for the Timer_A INCLK.

6.11.14 Real-Time Clock (RTC_A)

The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar mode integrates an internal calendar which compensates for months with less than 31 days and includes leap year correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.

6.11.15 REF Voltage Reference

The reference module (REF) is responsible for generation of all critical reference voltages that can be used by the various analog peripherals in the device. These include the ADC12_A, LCD_B, and COMP_B modules.

6.11.16 Comparator_B

The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals.

6.11.17 ADC12_A

The ADC12_A module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.

6.11.18 Embedded Emulation Module (EEM) (S Version)

The EEM supports real-time in-system debugging. The S version of the EEM has the following features:

  • Three hardware triggers or breakpoints on memory access
  • One hardware trigger or breakpoint on CPU register write access
  • Up to four hardware triggers can be combined to form complex triggers or breakpoints
  • One cycle counter
  • Clock control on module level

6.11.19 Peripheral File Map

Table 6-14 lists the register base address and offset range for each peripheral. Table 6-15 through Table 6-45 list the registers that are available in each peripheral.

Table 6-14 Peripherals

MODULE NAME BASE ADDRESS OFFSET ADDRESS RANGE
Special Functions (see Table 6-15) 0100h 000h-01Fh
PMM (see Table 6-16) 0120h 000h-00Fh
Flash Control (see Table 6-17) 0140h 000h-00Fh
CRC16 (see Table 6-18) 0150h 000h-007h
RAM Control (see Table 6-19) 0158h 000h-001h
Watchdog (see Table 6-20) 015Ch 000h-001h
UCS (see Table 6-21) 0160h 000h-01Fh
SYS (see Table 6-22) 0180h 000h-01Fh
Shared Reference (see Table 6-23) 01B0h 000h-001h
Port Mapping Control (see Table 6-24) 01C0h 000h-007h
Port Mapping Port P1 (see Table 6-25) 01C8h 000h-007h
Port Mapping Port P2 (see Table 6-26) 01D0h 000h-007h
Port Mapping Port P3 (see Table 6-27) 01D8h 000h-007h
Port P1, P2 (see Table 6-28) 0200h 000h-01Fh
Port P3, P4 (see Table 6-29) 0220h 000h-01Fh
Port P5 (see Table 6-30) 0240h 000h-01Fh
Port PJ (see Table 6-31) 0320h 000h-01Fh
TA0 (see Table 6-32) 0340h 000h-03Fh
TA1 (see Table 6-33) 0380h 000h-03Fh
RTC_A (see Table 6-34) 04A0h 000h-01Fh
32-Bit Hardware Multiplier (see Table 6-35) 04C0h 000h-02Fh
DMA Module Control (see Table 6-36) 0500h 000h-00Fh
DMA Channel 0 (see Table 6-37) 0510h 000h-00Fh
DMA Channel 1 (see Table 6-38) 0520h 000h-00Fh
DMA Channel 2 (see Table 6-39) 0530h 000h-00Fh
USCI_A0 (see Table 6-40) 05C0h 000h-01Fh
USCI_B0 (see Table 6-41) 05E0h 000h-01Fh
ADC12 (see Table 6-42) 0700h 000h-03Fh
Comparator_B (see Table 6-43) 08C0h 000h-00Fh
AES Accelerator (see Table 6-44) 09C0h 000h-00Fh
Radio Interface (see Table 6-45) 0F00h 000h-03Fh

Table 6-15 Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION REGISTER OFFSET
SFR interrupt enable SFRIE1 00h
SFR interrupt flag SFRIFG1 02h
SFR reset pin control SFRRPCR 04h

Table 6-16 PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION REGISTER OFFSET
PMM control 0 PMMCTL0 00h
PMM control 1 PMMCTL1 02h
SVS high-side control SVSMHCTL 04h
SVS low-side control SVSMLCTL 06h
PMM interrupt flags PMMIFG 0Ch
PMM interrupt enable PMMIE 0Eh
PMM power mode 5 control PM5CTL0 10h

Table 6-17 Flash Control Registers (Base Address: 0140h)

REGISTER DESCRIPTION REGISTER OFFSET
Flash control 1 FCTL1 00h
Flash control 3 FCTL3 04h
Flash control 4 FCTL4 06h

Table 6-18 CRC16 Registers (Base Address: 0150h)

REGISTER DESCRIPTION REGISTER OFFSET
CRC data input CRC16DI 00h
CRC data input reverse byte CRCDIRB 02h
CRC initialization and result CRCINIRES 04h
CRC result reverse byte CRCRESR 06h

Table 6-19 RAM Control Registers (Base Address: 0158h)

REGISTER DESCRIPTION REGISTER OFFSET
RAM control 0 RCCTL0 00h

Table 6-20 Watchdog Registers (Base Address: 015Ch)

REGISTER DESCRIPTION REGISTER OFFSET
Watchdog timer control WDTCTL 00h

Table 6-21 UCS Registers (Base Address: 0160h)

REGISTER DESCRIPTION REGISTER OFFSET
UCS control 0 UCSCTL0 00h
UCS control 1 UCSCTL1 02h
UCS control 2 UCSCTL2 04h
UCS control 3 UCSCTL3 06h
UCS control 4 UCSCTL4 08h
UCS control 5 UCSCTL5 0Ah
UCS control 6 UCSCTL6 0Ch
UCS control 7 UCSCTL7 0Eh
UCS control 8 UCSCTL8 10h

Table 6-22 SYS Registers (Base Address: 0180h)

REGISTER DESCRIPTION REGISTER OFFSET
System control SYSCTL 00h
Bootloader configuration area SYSBSLC 02h
JTAG mailbox control SYSJMBC 06h
JTAG mailbox input 0 SYSJMBI0 08h
JTAG mailbox input 1 SYSJMBI1 0Ah
JTAG mailbox output 0 SYSJMBO0 0Ch
JTAG mailbox output 1 SYSJMBO1 0Eh
Bus error vector generator SYSBERRIV 18h
User NMI vector generator SYSUNIV 1Ah
System NMI vector generator SYSSNIV 1Ch
Reset vector generator SYSRSTIV 1Eh

Table 6-23 Shared Reference Registers (Base Address: 01B0h)

REGISTER DESCRIPTION REGISTER OFFSET
Shared reference control REFCTL 00h

Table 6-24 Port Mapping Control Registers (Base Address: 01C0h)

REGISTER DESCRIPTION REGISTER OFFSET
Port mapping key register PMAPKEYID 00h
Port mapping control register PMAPCTL 02h

Table 6-25 Port Mapping Port P1 Registers (Base Address: 01C8h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P1.0 mapping register P1MAP0 00h
Port P1.1 mapping register P1MAP1 01h
Port P1.2 mapping register P1MAP2 02h
Port P1.3 mapping register P1MAP3 03h
Port P1.4 mapping register P1MAP4 04h
Port P1.5 mapping register P1MAP5 05h
Port P1.6 mapping register P1MAP6 06h
Port P1.7 mapping register P1MAP7 07h

Table 6-26 Port Mapping Port P2 Registers (Base Address: 01D0h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P2.0 mapping register P2MAP0 00h
Port P2.1 mapping register P2MAP2 01h
Port P2.2 mapping register P2MAP2 02h
Port P2.3 mapping register P2MAP3 03h
Port P2.4 mapping register P2MAP4 04h
Port P2.5 mapping register P2MAP5 05h
Port P2.6 mapping register P2MAP6 06h
Port P2.7 mapping register P2MAP7 07h

Table 6-27 Port Mapping Port P3 Registers (Base Address: 01D8h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P3.0 mapping register P3MAP0 00h
Port P3.1 mapping register P3MAP3 01h
Port P3.2 mapping register P3MAP2 02h
Port P3.3 mapping register P3MAP3 03h
Port P3.4 mapping register P3MAP4 04h
Port P3.5 mapping register P3MAP5 05h
Port P3.6 mapping register P3MAP6 06h
Port P3.7 mapping register P3MAP7 07h

Table 6-28 Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P1 input P1IN 00h
Port P1 output P1OUT 02h
Port P1 direction P1DIR 04h
Port P1 pullup or pulldown enable P1REN 06h
Port P1 drive strength P1DS 08h
Port P1 selection P1SEL 0Ah
Port P1 interrupt vector word P1IV 0Eh
Port P1 interrupt edge select P1IES 18h
Port P1 interrupt enable P1IE 1Ah
Port P1 interrupt flag P1IFG 1Ch
Port P2 input P2IN 01h
Port P2 output P2OUT 03h
Port P2 direction P2DIR 05h
Port P2 pullup or pulldown enable P2REN 07h
Port P2 drive strength P2DS 09h
Port P2 selection P2SEL 0Bh
Port P2 interrupt vector word P2IV 1Eh
Port P2 interrupt edge select P2IES 19h
Port P2 interrupt enable P2IE 1Bh
Port P2 interrupt flag P2IFG 1Dh

Table 6-29 Port P3, P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P3 input P3IN 00h
Port P3 output P3OUT 02h
Port P3 direction P3DIR 04h
Port P3 pullup or pulldown enable P3REN 06h
Port P3 drive strength P3DS 08h
Port P3 selection P3SEL 0Ah

Table 6-30 Port P5 Registers (Base Address: 0240h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P5 input P5IN 00h
Port P5 output P5OUT 02h
Port P5 direction P5DIR 04h
Port P5 pullup or pulldown enable P5REN 06h
Port P5 drive strength P5DS 08h
Port P5 selection P5SEL 0Ah

Table 6-31 Port J Registers (Base Address: 0320h)

REGISTER DESCRIPTION REGISTER OFFSET
Port PJ input PJIN 00h
Port PJ output PJOUT 02h
Port PJ direction PJDIR 04h
Port PJ pullup or pulldown enable PJREN 06h
Port PJ drive strength PJDS 08h

Table 6-32 TA0 Registers (Base Address: 0340h)

REGISTER DESCRIPTION REGISTER OFFSET
TA0 control TA0CTL 00h
Capture/compare control 0 TA0CCTL0 02h
Capture/compare control 1 TA0CCTL1 04h
Capture/compare control 2 TA0CCTL2 06h
Capture/compare control 3 TA0CCTL3 08h
Capture/compare control 4 TA0CCTL4 0Ah
TA0 counter TA0R 10h
Capture/compare register 0 TA0CCR0 12h
Capture/compare register 1 TA0CCR1 14h
Capture/compare register 2 TA0CCR2 16h
Capture/compare register 3 TA0CCR3 18h
Capture/compare register 4 TA0CCR4 1Ah
TA0 expansion register 0 TA0EX0 20h
TA0 interrupt vector TA0IV 2Eh

Table 6-33 TA1 Registers (Base Address: 0380h)

REGISTER DESCRIPTION REGISTER OFFSET
TA1 control TA1CTL 00h
Capture/compare control 0 TA1CCTL0 02h
Capture/compare control 1 TA1CCTL1 04h
Capture/compare control 2 TA1CCTL2 06h
TA1 counter TA1R 10h
Capture/compare register 0 TA1CCR0 12h
Capture/compare register 1 TA1CCR1 14h
Capture/compare register 2 TA1CCR2 16h
TA1 expansion register 0 TA1EX0 20h
TA1 interrupt vector TA1IV 2Eh

Table 6-34 Real-Time Clock Registers (Base Address: 04A0h)

REGISTER DESCRIPTION REGISTER OFFSET
RTC control 0 RTCCTL0 00h
RTC control 1 RTCCTL1 01h
RTC control 2 RTCCTL2 02h
RTC control 3 RTCCTL3 03h
RTC prescaler 0 control RTCPS0CTL 08h
RTC prescaler 1 control RTCPS1CTL 0Ah
RTC prescaler 0 RTCPS0 0Ch
RTC prescaler 1 RTCPS1 0Dh
RTC interrupt vector word RTCIV 0Eh
RTC seconds/counter register 1 RTCSEC/RTCNT1 10h
RTC minutes/counter register 2 RTCMIN/RTCNT2 11h
RTC hours/counter register 3 RTCHOUR/RTCNT3 12h
RTC day of week/counter register 4 RTCDOW/RTCNT4 13h
RTC days RTCDAY 14h
RTC month RTCMON 15h
RTC year low RTCYEARL 16h
RTC year high RTCYEARH 17h
RTC alarm minutes RTCAMIN 18h
RTC alarm hours RTCAHOUR 19h
RTC alarm day of week RTCADOW 1Ah
RTC alarm days RTCADAY 1Bh

Table 6-35 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

REGISTER DESCRIPTION REGISTER OFFSET
16-bit operand 1 – multiply MPY 00h
16-bit operand 1 – signed multiply MPYS 02h
16-bit operand 1 – multiply accumulate MAC 04h
16-bit operand 1 – signed multiply accumulate MACS 06h
16-bit operand 2 OP2 08h
16 × 16 result low word RESLO 0Ah
16 × 16 result high word RESHI 0Ch
16 × 16 sum extension register SUMEXT 0Eh
32-bit operand 1 – multiply low word MPY32L 10h
32-bit operand 1 – multiply high word MPY32H 12h
32-bit operand 1 – signed multiply low word MPYS32L 14h
32-bit operand 1 – signed multiply high word MPYS32H 16h
32-bit operand 1 – multiply accumulate low word MAC32L 18h
32-bit operand 1 – multiply accumulate high word MAC32H 1Ah
32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch
32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh
32-bit operand 2 – low word OP2L 20h
32-bit operand 2 – high word OP2H 22h
32 × 32 result 0 – least significant word RES0 24h
32 × 32 result 1 RES1 26h
32 × 32 result 2 RES2 28h
32 × 32 result 3 – most significant word RES3 2Ah
MPY32 control register 0 MPY32CTL0 2Ch

Table 6-36 DMA Module Control Registers (Base Address: 0500h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA module control 0 DMACTL0 00h
DMA module control 1 DMACTL1 02h
DMA module control 2 DMACTL2 04h
DMA module control 3 DMACTL3 06h
DMA module control 4 DMACTL4 08h
DMA interrupt vector DMAIV 0Ah

Table 6-37 DMA Channel 0 Registers (Base Address: 0510h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 0 control DMA0CTL 00h
DMA channel 0 source address low DMA0SAL 02h
DMA channel 0 source address high DMA0SAH 04h
DMA channel 0 destination address low DMA0DAL 06h
DMA channel 0 destination address high DMA0DAH 08h
DMA channel 0 transfer size DMA0SZ 0Ah

Table 6-38 DMA Channel 1 Registers (Base Address: 0520h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 1 control DMA1CTL 00h
DMA channel 1 source address low DMA1SAL 02h
DMA channel 1 source address high DMA1SAH 04h
DMA channel 1 destination address low DMA1DAL 06h
DMA channel 1 destination address high DMA1DAH 08h
DMA channel 1 transfer size DMA1SZ 0Ah

Table 6-39 DMA Channel 2 Registers (Base Address: 0530h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 2 control DMA2CTL 00h
DMA channel 2 source address low DMA2SAL 02h
DMA channel 2 source address high DMA2SAH 04h
DMA channel 2 destination address low DMA2DAL 06h
DMA channel 2 destination address high DMA2DAH 08h
DMA channel 2 transfer size DMA2SZ 0Ah

Table 6-40 USCI_A0 Registers (Base Address: 05C0h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI control 1 UCA0CTL1 00h
USCI control 0 UCA0CTL0 01h
USCI baud rate 0 UCA0BR0 06h
USCI baud rate 1 UCA0BR1 07h
USCI modulation control UCA0MCTL 08h
USCI status UCA0STAT 0Ah
USCI receive buffer UCA0RXBUF 0Ch
USCI transmit buffer UCA0TXBUF 0Eh
USCI LIN control UCA0ABCTL 10h
USCI IrDA transmit control UCA0IRTCTL 12h
USCI IrDA receive control UCA0IRRCTL 13h
USCI interrupt enable UCA0IE 1Ch
USCI interrupt flags UCA0IFG 1Dh
USCI interrupt vector word UCA0IV 1Eh

Table 6-41 USCI_B0 Registers (Base Address: 05E0h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI synchronous control 1 UCB0CTL1 00h
USCI synchronous control 0 UCB0CTL0 01h
USCI synchronous bit rate 0 UCB0BR0 06h
USCI synchronous bit rate 1 UCB0BR1 07h
USCI synchronous status UCB0STAT 0Ah
USCI synchronous receive buffer UCB0RXBUF 0Ch
USCI synchronous transmit buffer UCB0TXBUF 0Eh
USCI I2C own address UCB0I2COA 10h
USCI I2C slave address UCB0I2CSA 12h
USCI interrupt enable UCB0IE 1Ch
USCI interrupt flags UCB0IFG 1Dh
USCI interrupt vector word UCB0IV 1Eh

Table 6-42 ADC12_A Registers (Base Address: 0700h)

REGISTER DESCRIPTION REGISTER OFFSET
Control register 0 ADC12CTL0 00h
Control register 1 ADC12CTL1 02h
Control register 2 ADC12CTL2 04h
Interrupt-flag register ADC12IFG 0Ah
Interrupt-enable register ADC12IE 0Ch
Interrupt-vector-word register ADC12IV 0Eh
ADC memory-control register 0 ADC12MCTL0 10h
ADC memory-control register 1 ADC12MCTL1 11h
ADC memory-control register 2 ADC12MCTL2 12h
ADC memory-control register 3 ADC12MCTL3 13h
ADC memory-control register 4 ADC12MCTL4 14h
ADC memory-control register 5 ADC12MCTL5 15h
ADC memory-control register 6 ADC12MCTL6 16h
ADC memory-control register 7 ADC12MCTL7 17h
ADC memory-control register 8 ADC12MCTL8 18h
ADC memory-control register 9 ADC12MCTL9 19h
ADC memory-control register 10 ADC12MCTL10 1Ah
ADC memory-control register 11 ADC12MCTL11 1Bh
ADC memory-control register 12 ADC12MCTL12 1Ch
ADC memory-control register 13 ADC12MCTL13 1Dh
ADC memory-control register 14 ADC12MCTL14 1Eh
ADC memory-control register 15 ADC12MCTL15 1Fh
Conversion memory 0 ADC12MEM0 20h
Conversion memory 1 ADC12MEM1 22h
Conversion memory 2 ADC12MEM2 24h
Conversion memory 3 ADC12MEM3 26h
Conversion memory 4 ADC12MEM4 28h
Conversion memory 5 ADC12MEM5 2Ah
Conversion memory 6 ADC12MEM6 2Ch
Conversion memory 7 ADC12MEM7 2Eh
Conversion memory 8 ADC12MEM8 30h
Conversion memory 9 ADC12MEM9 32h
Conversion memory 10 ADC12MEM10 34h
Conversion memory 11 ADC12MEM11 36h
Conversion memory 12 ADC12MEM12 38h
Conversion memory 13 ADC12MEM13 3Ah
Conversion memory 14 ADC12MEM14 3Ch
Conversion memory 15 ADC12MEM15 3Eh

Table 6-43 Comparator_B Registers (Base Address: 08C0h)

REGISTER DESCRIPTION REGISTER OFFSET
Comp_B control register 0 CBCTL0 00h
Comp_B control register 1 CBCTL1 02h
Comp_B control register 2 CBCTL2 04h
Comp_B control register 3 CBCTL3 06h
Comp_B interrupt register CBINT 0Ch
Comp_B interrupt vector word CBIV 0Eh

Table 6-44 AES Accelerator Registers (Base Address: 09C0h)

REGISTER DESCRIPTION REGISTER OFFSET
AES accelerator control register 0 AESACTL0 00h
Reserved 02h
AES accelerator status register AESASTAT 04h
AES accelerator key register AESAKEY 06h
AES accelerator data in register AESADIN 008h
AES accelerator data out register AESADOUT 00Ah

Table 6-45 Radio Interface Registers (Base Address: 0F00h)

REGISTER DESCRIPTION REGISTER OFFSET
Radio interface control 0 RF1AIFCTL0 00h
Radio interface control 1 RF1AIFCTL1 02h
Radio interface error flag RF1AIFERR 06h
Radio interface error vector word RF1AIFERRV 0Ch
Radio interface interrupt vector word RF1AIFIV 0Eh
Radio instruction word RF1AINSTRW 10h
Radio instruction word, 1-byte auto-read RF1AINSTR1W 12h
Radio instruction word, 2-byte auto-read RF1AINSTR2W 14h
Radio data in register RF1ADINW 16h
Radio status word RF1ASTATW 20h
Radio status word, 1-byte auto-read RF1ASTAT1W 22h
Radio status word, 2-byte auto-read RF1AISTAT2W 24h
Radio data out RF1ADOUTW 28h
Radio data out, 1-byte auto-read RF1ADOUT1W 2Ah
Radio data out, 2-byte auto-read RF1ADOUT2W 2Ch
Radio core signal input RF1AIN 30h
Radio core interrupt flag RF1AIFG 32h
Radio core interrupt edge select RF1AIES 34h
Radio core interrupt enable RF1AIE 36h
Radio core interrupt vector word RF1AIV 38h

6.12 Input/Output Schematics

6.12.1 Port P1, P1.0 to P1.4, Input/Output With Schmitt Trigger

Figure 6-3 shows the port schematic, and Table 6-46 summarizes selection of the pin function.

RF430F5978 p1_01234_slas740.gif Figure 6-3 Port P1 (P1.0 to P1.4) Schematic

Table 6-46 Port P1 (P1.0 to P1.4) Pin Functions

PIN NAME (P1.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P1DIR.x P1SEL.x P1MAPx LCDS19 to LCDS22
P1.0/P1MAP/S18 0 P1.0 (I/O) I: 0; O: 1 0 X 0
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2) 0
Output driver and input Schmitt trigger disabled X 1 = 31 0
S18 X X X 1
P1.1/P1MAP1/S19 1 P1.1 (I/O) I: 0; O: 1 0 X 0
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2) 0
Output driver and input Schmitt trigger disabled X 1 = 31 0
S19 X X X 1
P1.2/P1MAP2/S20 2 P1.2 (I/O) I: 0; O: 1 0 X 0
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2) 0
Output driver and input Schmitt trigger disabled X 1 = 31 0
S22 X X X 1
P1.3/P1MAP3/S21 3 P1.3 (I/O) I: 0; O: 1 0 X 0
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2) 0
Output driver and input Schmitt trigger disabled X 1 = 31 0
S21 X X X 1
P1.4/P1MAP4/S22 4 P1.4 (I/O) I: 0; O: 1 0 X 0
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2) 0
Output driver and input Schmitt trigger disabled X 1 = 31 0
S22 X X X 1
(1) X = don't care
(2) According to mapped function - see Table 6-8.

6.12.2 Port P1, P1.5 to P1.7, Input/Output With Schmitt Trigger

Figure 6-4 shows the port schematic, and Table 6-47 summarizes selection of the pin function.

RF430F5978 p1_567_slas740.gif Figure 6-4 Port P1 (P1.5 to P1.7) Schematic

Table 6-47 Port P1 (P1.5 to P1.7) Pin Functions

PIN NAME (P1.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P1DIR.x P1SEL.x P1MAPx
P1.5/P1MAP5/R23 5 P1.5 (I/O) I: 0; O: 1 0 X
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2)
R23(1) X 1 = 31
P1.6/P1MAP6/R13/ LCDREF 6 P1.6 (I/O) I: 0; O: 1 0 X
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2)
R13/LCDREF(1) X 1 = 31
P1.7/P1MAP7/R03 7 P1.7 (I/O) I: 0; O: 1 0 X
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2)
R03(1) X 1 = 31
(1) Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.

6.12.3 Port P2, P2.0 to P2.2, Input/Output With Schmitt Trigger

Figure 6-5 shows the port schematic, and Table 6-48 summarizes selection of the pin function.

RF430F5978 p2_0123_slas740.gif Figure 6-5 Port P2 (P2.0 to P2.2) Schematic

6.12.4 Port P2, P2.4 and P2.5, Input/Output With Schmitt Trigger

Figure 6-6 shows the port schematic, and Table 6-48 summarizes selection of the pin function.

RF430F5978 p2_45_slas740.gif Figure 6-6 Port P2 (P2.4 and P2.5) Schematic

Table 6-48 Port P2 (P2.0 to P2.2, P2.4, and P2.5) Pin Functions

PIN NAME (P2.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P2DIR.x P2SEL.x P2MAPx CBPD.x
P2.0/P2MAP0/CB0 (/A0) 0 P2.0 (I/O) I: 0; O: 1 0 X 0
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2) 0
A0(1) X 1 = 31 X
CB0(2) X X X 1
P2.1/P2MAP1/CB1 (/A1) 1 P2.1 (I/O) I: 0; O: 1 0 X 0
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2) 0
A1(1) X 1 = 31 X
CB1(2) X X X 1
P2.2/P2MAP2/CB2 (/A2) 2 P2.2 (I/O) I: 0; O: 1 0 X 0
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2) 0
A2(1) X 1 = 31 X
CB2(2) X X X 1
P2.4/P2MAP4/CB4 (/A4/VREF-/VeREF-) 4 P2.4 (I/O) I: 0; O: 1 0 X 0
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2) 0
A4/VREF-/VeREF-(1) X 1 = 31 X
CB4(2) X X X 1
P2.5/P2MAP5/CB5 (/A5/VREF+/VeREF+) 5 P2.5 (I/O) I: 0; O: 1 0 X 0
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2) 0
A5/VREF+/VeREF+(1) X 1 = 31 X
CB5(2) X X X 1
(1) Setting P2SEL.x bit together with P2MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.
(2) Setting the CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input buffer for that pin, regardless of the state of the associated CBPD.x bit.

6.12.5 Port P3, P3.1 to P3.3, P3.5, and P3.7, Input/Output With Schmitt Trigger

Figure 6-7 shows the port schematic, and Table 6-49 summarizes selection of the pin function.

RF430F5978 p3_01234567_slas740.gif Figure 6-7 Port P3 (P3.1 to P3.3, P3.5, and P3.7) Schematic

Table 6-49 Port P3 (P3.1 to P3.3, P3.5, and P3.7) Pin Functions

PIN NAME (P3.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P3DIR.x P3SEL.x P3MAPx LCDS10 to LCDS17
P3.1/P3MAP1/S11(1) 1 P3.1 (I/O) I: 0; O: 1 0 X 0
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2) 0
Output driver and input Schmitt trigger disabled X 1 = 31 0
S11 X X X 1
P3.2/P3MAP7/S12(1) 2 P3.2 (I/O) I: 0; O: 1 0 X 0
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2) 0
Output driver and input Schmitt trigger disabled X 1 = 31 0
S12 X X X 1
P3.3/P3MAP3/S13(1) 3 P3.3 (I/O) I: 0; O: 1 0 X 0
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2) 0
Output driver and input Schmitt trigger disabled X 1 = 31 0
S13 X X X 1
P3.5/P3MAP5/S15(1) 5 P3.5 (I/O) I: 0; O: 1 0 X 0
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2) 0
Output driver and input Schmitt trigger disabled X 1 = 31 0
S15 X X X 1
S16 X X X 1
P3.7/P3MAP7/S17 7 P3.7 (I/O) I: 0; O: 1 0 X 0
Mapped secondary digital function - see Table 6-8 0; 1(2) 1 ≤ 30(2) 0
Output driver and input Schmitt trigger disabled X 1 = 31 0
S17 X X X 1
(1) Internal connection to LF front end

6.12.6 Port P4, P4.0 to P4.2, Input/Output With Schmitt Trigger

Figure 6-8 shows the port schematic, and Table 6-50 summarizes selection of the pin function.

RF430F5978 p4_01234567_slas740.gif Figure 6-8 Port P4 (P4.0 to P4.2) Schematic

Table 6-50 Port P4 (P4.0 to P4.2) Pin Functions

PIN NAME (P4.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P4DIR.x P4SEL.x LCDS2 to LCDS7
P4.0/P4MAP0/S2 0 P4.0 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S2 X X 1
P4.1/P4MAP1/S3(1) 1 P4.1 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S3 X X 1
P4.2/P4MAP7/S4(1) 2 P4.2 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S4 X X 1

6.12.7 Port P5, P5.0, Input/Output With Schmitt Trigger

Figure 6-9 shows the port schematic, and Table 6-51 summarizes selection of the pin function.

RF430F5978 p5_0_slas740.gif Figure 6-9 Port P5 (P5.0) Schematic

6.12.8 Port P5, P5.1, Input/Output With Schmitt Trigger

Figure 6-10 shows the port schematic, and Table 6-51 summarizes selection of the pin function.

RF430F5978 p5_1_slas740.gif Figure 6-10 Port P5 (P5.1) Schematic

Table 6-51 Port P5 (P5.0 and P5.1) Pin Functions

PIN NAME (P5.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P5DIR.x P5SEL.0 P5SEL.1 XT1BYPASS
P5.0/XIN 0 P5.0 (I/O) I: 0; O: 1 0 X X
XIN crystal mode(1) X 1 X 0
XIN bypass mode(1) X 1 X 1
P5.1/XOUT 1 P5.1 (I/O) I: 0; O: 1 0 X X
XOUT crystal mode(2) X 1 X 0
P5.1 (I/O)(2) X 1 X 1
(1) Setting P5SEL.0 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.0 is configured for crystal mode or bypass mode.
(2) Setting P5SEL.0 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.1 can be used as general-purpose I/O.

6.12.9 Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output

Figure 6-11 shows the port schematic, and Table 6-52 summarizes selection of the pin function.

RF430F5978 pj_0_slas740.gif Figure 6-11 Port PJ (PJ.0) Schematic

6.12.10 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output

Figure 6-12 shows the port schematic, and Table 6-52 summarizes selection of the pin function.

RF430F5978 pj_123_slas740.gif Figure 6-12 Port PJ (PJ.1 to PJ.3) Schematic

Table 6-52 Port PJ (PJ.0 to PJ.3) Pin Functions

PIN NAME (PJ.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
PJDIR.x
PJ.0/TDO 0 PJ.0 (I/O)(1) I: 0; O: 1
TDO(2) X
PJ.1/TDI/TCLK 1 PJ.1 (I/O)(1) I: 0; O: 1
TDI/TCLK(2) (3) X
PJ.2/TMS 2 PJ.2 (I/O)(1) I: 0; O: 1
TMS(2) (3) X
PJ.3/TCK 3 PJ.3 (I/O)(1) I: 0; O: 1
TCK(2) (3) X
(1) Default condition
(2) The pin direction is controlled by the JTAG module.
(3) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.

6.13 Device Descriptor Structures

Table 6-53 lists the content of the device descriptor tag-length-value (TLV) structure.

Table 6-53 Device Descriptor Table

DESCRIPTION ADDRESS SIZE
(bytes)		 VALUE
RF430F5978
Info Block Info length 01A00h 1 06h
CRC length 01A01h 1 06h
CRC value 01A02h 2 per unit
Device ID 01A04h 1 61h
Device ID 01A05h 1 37h
Hardware revision 01A06h 1 per unit
Firmware revision 01A07h 1 per unit
Die Record Die record tag 01A08h 1 08h
Die record length 01A09h 1 0Ah
Lot/wafer ID 01A0Ah 4 per unit
Die X position 01A0Eh 2 per unit
Die Y position 01A10h 2 per unit
Test results 01A12h 2 per unit
ADC12 Calibration ADC12 calibration tag 01A14h 1 11h
ADC12 calibration length 01A15h 1 10h
ADC gain factor 01A16h 2 per unit
ADC offset 01A18h 2 per unit
ADC 1.5-V reference
Temperature sensor 30°C		 01A1Ah 2 per unit
ADC 1.5-V reference
Temperature sensor 85°C		 01A1Ch 2 per unit
ADC 2.0-V reference
Temperature sensor 30°C		 01A1Eh 2 per unit
ADC 2.0-V reference
Temperature sensor 85°C		 01A20h 2 per unit
ADC 2.5-V reference
Temperature sensor 30°C		 01A22h 2 per unit
ADC 2.5-V reference
Temperature sensor 85°C		 01A24h 2 per unit
REF Calibration REF calibration tag 01A26h 1 12h
REF calibration length 01A27h 1 06h
1.5-V reference factor 01A28h 2 per unit
2.0-V reference factor 01A2Ah 2 per unit
2.5-V reference factor 01A2Ch 2 per unit
Peripheral Descriptor (PD) Peripheral descriptor tag 01A2Eh 1 02h
Peripheral descriptor length 01A2Fh 1 57h
Peripheral descriptors 01A30h PD Length ...