SLAS740A January   2013  – October 2015 RF430F5978

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics - Active Mode Supply Currents
    6. 5.6  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Typical Characteristics - Low-Power Mode Supply Currents
    8. 5.8  Thermal Resistance Characteristics
    9. 5.9  Digital Inputs
    10. 5.10 Digital Outputs
    11. 5.11 Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
    12. 5.12 Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
    13. 5.13 Crystal Oscillator, XT1, Low-Frequency Mode
    14. 5.14 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    15. 5.15 Internal Reference, Low-Frequency Oscillator (REFO)
    16. 5.16 DCO Frequency
    17. 5.17 PMM, Brown-Out Reset (BOR)
    18. 5.18 PMM, Core Voltage
    19. 5.19 PMM, SVS High Side
    20. 5.20 PMM, SVM High Side
    21. 5.21 PMM, SVS Low Side
    22. 5.22 PMM, SVM Low Side
    23. 5.23 Wake-up Times From Low-Power Modes and Reset
    24. 5.24 Timer_A
    25. 5.25 USCI (UART Mode) Clock Frequency
    26. 5.26 USCI (UART Mode)
    27. 5.27 USCI (SPI Master Mode) Clock Frequency
    28. 5.28 USCI (SPI Master Mode)
    29. 5.29 USCI (SPI Slave Mode)
    30. 5.30 USCI (I2C Mode)
    31. 5.31 12-Bit ADC, Power Supply and Input Range Conditions
    32. 5.32 12-Bit ADC, Timing Parameters
    33. 5.33 12-Bit ADC, Linearity Parameters
    34. 5.34 12-Bit ADC, Temperature Sensor and Built-In VMID
    35. 5.35 REF, External Reference
    36. 5.36 REF, Built-In Reference
    37. 5.37 Comparator B
    38. 5.38 Flash Memory
    39. 5.39 JTAG and Spy-Bi-Wire Interface
    40. 5.40 RF1A CC1101 Radio Parameters
      1. 5.40.1  RF Crystal Oscillator, XT2
      2. 5.40.2  Current Consumption, Reduced-Power Modes
      3. 5.40.3  Current Consumption, Receive Mode
      4. 5.40.4  Current Consumption, Transmit Mode
      5. 5.40.5  Typical TX Current Consumption, 315 MHz
      6. 5.40.6  Typical TX Current Consumption, 433 MHz
      7. 5.40.7  Typical TX Current Consumption, 868 MHz
      8. 5.40.8  Typical TX Current Consumption, 915 MHz
      9. 5.40.9  RF Receive, Overall
      10. 5.40.10 RF Receive, 315 MHz
      11. 5.40.11 RF Receive, 433 MHz
      12. 5.40.12 RF Receive, 868 or 915 MHz
      13. 5.40.13 Typical Sensitivity, 315 MHz, Sensitivity-Optimized Setting
      14. 5.40.14 Typical Sensitivity, 433 MHz, Sensitivity-Optimized Setting
      15. 5.40.15 Typical Sensitivity, 868 MHz, Sensitivity-Optimized Setting
      16. 5.40.16 Typical Sensitivity, 915 MHz, Sensitivity-Optimized Setting
      17. 5.40.17 RF Transmit
      18. 5.40.18 Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
      19. 5.40.19 Typical Output Power, 315 MHz
      20. 5.40.20 Typical Output Power, 433 MHz
      21. 5.40.21 Typical Output Power, 868 MHz
      22. 5.40.22 Typical Output Power, 915 MHz
      23. 5.40.23 Frequency Synthesizer Characteristics
      24. 5.40.24 Typical RSSI_offset Values
    41. 5.41 3D LF Front-End Parameters
      1. 5.41.1 Recommended Operating Conditions
      2. 5.41.2 Resonant Circuits - LF Front End
      3. 5.41.3 External Antenna Coil - LF Front End
      4. 5.41.4 Resonant Circuit Capacitor - LF Front End
      5. 5.41.5 Charge Capacitor - LF Front End
      6. 5.41.6 LF Wake Receiver Electrical Characteristics
      7. 5.41.7 RSSI - LF Wake Receiver Electrical Characteristics
  6. 6Detailed Description
    1. 6.1  3D LF Wake Receiver and 3D Transponder Interface
      1. 6.1.1 3D LF Front End
      2. 6.1.2 EEPROM
      3. 6.1.3 Switch Interface
    2. 6.2  Sub-1-GHz Radio
    3. 6.3  CPU
    4. 6.4  Operating Modes
    5. 6.5  Interrupt Vector Addresses
    6. 6.6  Memory Organization
    7. 6.7  Bootloader (BSL)
    8. 6.8  JTAG Operation
      1. 6.8.1 JTAG Standard Interface
      2. 6.8.2 Spy-Bi-Wire Interface
    9. 6.9  Flash Memory
    10. 6.10 RAM
    11. 6.11 Peripherals
      1. 6.11.1  Oscillator and System Clock
      2. 6.11.2  Power-Management Module (PMM)
      3. 6.11.3  Digital I/O
      4. 6.11.4  Port Mapping Controller
      5. 6.11.5  System (SYS) Module
      6. 6.11.6  DMA Controller
      7. 6.11.7  Watchdog Timer (WDT_A)
      8. 6.11.8  CRC16
      9. 6.11.9  Hardware Multiplier
      10. 6.11.10 AES128 Accelerator
      11. 6.11.11 Universal Serial Communication Interface (USCI)
      12. 6.11.12 TA0
      13. 6.11.13 TA1
      14. 6.11.14 Real-Time Clock (RTC_A)
      15. 6.11.15 REF Voltage Reference
      16. 6.11.16 Comparator_B
      17. 6.11.17 ADC12_A
      18. 6.11.18 Embedded Emulation Module (EEM) (S Version)
      19. 6.11.19 Peripheral File Map
    12. 6.12 Input/Output Schematics
      1. 6.12.1  Port P1, P1.0 to P1.4, Input/Output With Schmitt Trigger
      2. 6.12.2  Port P1, P1.5 to P1.7, Input/Output With Schmitt Trigger
      3. 6.12.3  Port P2, P2.0 to P2.2, Input/Output With Schmitt Trigger
      4. 6.12.4  Port P2, P2.4 and P2.5, Input/Output With Schmitt Trigger
      5. 6.12.5  Port P3, P3.1 to P3.3, P3.5, and P3.7, Input/Output With Schmitt Trigger
      6. 6.12.6  Port P4, P4.0 to P4.2, Input/Output With Schmitt Trigger
      7. 6.12.7  Port P5, P5.0, Input/Output With Schmitt Trigger
      8. 6.12.8  Port P5, P5.1, Input/Output With Schmitt Trigger
      9. 6.12.9  Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      10. 6.12.10 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    13. 6.13 Device Descriptor Structures
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Circuit
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Getting Started and Next Steps
      2. 8.1.2 Device and Development Tool Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Community Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Export Control Notice
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Terminal Configuration and Functions

4.1 Pin Diagram

Figure 4-1 shows the pinout of the 64-pin RGC package.

RF430F5978 pinout_rgc64_f59xx_slas740.gif

NOTE:

The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows the default mapping. See Table 6-8 for details.
Figure 4-1 64-Pin RGC Package (Top View)

4.2 Signal Descriptions

Table 4-1 describes the signals.

Table 4-1 Terminal Functions

TERMINAL I/O(1) DESCRIPTION
NAME NO.
P2.0/PM_CBOUT1/PM_TA1CLK/ CB0/A0 1 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: Comparator_B output

Default mapping: Timer1_A3 clock input

Comparator input CB0

Analog input A0 – 12-bit ADC
P1.7/ PM_UCA0CLK/PM_UCB0STE 2 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_A0 clock input/output

Default mapping: USCI_B0 SPI slave transmit enable
P1.6/ PM_UCA0TXD/PM_UCA0SIMO 3 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_A0 UART transmit data

Default mapping: USCI_A0 SPI slave in/master out
P1.5/ PM_UCA0RXD/PM_UCA0SOMI 4 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_A0 UART receive data

Default mapping: USCI_A0 SPI slave out/master in
VCORE 5 S Regulated core power supply
DVCC 6 S Digital power supply
P1.4/ PM_UCB0CLK/PM_UCA0STE 7 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 clock input/output

Default mapping: USCI_A0 SPI slave transmit enable
P1.3/ PM_UCB0SIMO/PM_UCB0SDA 8 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave in/master out

Default mapping: USCI_B0 I2C data
P1.2/ PM_UCB0SOMI/PM_UCB0SCL 9 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave out/master in

Default mapping: UCSI_B0 I2C clock
P1.1/PM_RFGDO2 10 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: Radio GDO2 output
P1.0/PM_RFGDO0 11 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: Radio GDO0 output
P3.7/PM_SMCLK 12 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: SMCLK output
AFE_VCL 13 A Charge capacitor and supply voltage for immobilizer mode
AFE_RF1 14 A Connection for resonant circuit 1
AFE_RF2 15 A Connection for resonant circuit 2
AFE_RF3 16 A Connection for resonant circuit 3
AFE_GND 17 Analog LF front end GND
AFE_TEN 18 I Test interface enable of analog LF front end
AFE_TDAT 19 I/O Test interface data of analog LF front end
AFE_TCLK 20 I Test interface clock of analog LF front end
AFE_ACTI 21 A Test interface output of analog front end
AFE_VCCSW 22 A Switched power supply buffer (external capacitor)
VBAT 23 S Supply voltage analog front end
GNDA 24 G Analog ground
WAKE 25 O Analog ground
NC 26 Not connected
SW0 27 I Switch input with internal pullup resistor
SW1 28 I Switch input with internal pullup resistor
SW2 29 I Switch input with internal pullup resistor
SW3 30 I Switch input with internal pullup resistor
SW4 31 I Switch input with internal pullup resistor
NC 32 Not connected
P4.0 33 I/O General-purpose digital I/O
SW5 34 I Switch input with internal pullup resistor
SW6 35 I Switch input with internal pullup resistor
SW7 36 I Switch input with internal pullup resistor
RF_XIN 37 I Input terminal for RF crystal oscillator or external clock input
RF_XOUT 38 O Output terminal for RF crystal oscillator
RF_AVCC 39 S Radio analog power supply
RF_GND 40 G Radio ground
RF_AVCC 41 S Radio analog power supply
RF_GND 42 G Radio ground
RF_P 43 RF I/O Positive RF input to LNA in receive mode

Positive RF output from PA in transmit mode
RF_N 44 RF I/O Negative RF input to LNA in receive mode

Negative RF output from PA in transmit mode
RF_GND 45 G Radio ground
RF_AVCC 46 S Radio analog power supply
RF_RBIAS 47 External bias resistor for radio reference current
RF_AVCC 48 I/O Radio analog power supply
PJ.0/TDO 49 I/O General-purpose digital I/O or test data output port
PJ.1/TDI/TCLK 50 I/O General-purpose digital I/O or test data input or test clock input
PJ.2/TMS 51 I/O General-purpose digital I/O or test mode select
PJ.3/TCK 52 I/O General-purpose digital I/O or test clock
TEST/SBWTCK 53 I Test mode pin – select digital I/O on JTAG pins or Spy-Bi-Wire input clock
RST/NMI/SBWTDIO 54 I/O Reset input active low

Nonmaskable interrupt input

Spy-Bi-Wire data input/output
DVCC 55 S Digital power supply
DGND 56 G Digital ground supply
AGND 57 G Analog ground supply
P5.1/XOUT 58 I/O General-purpose digital I/O

Output terminal of crystal oscillator XT1
P5.0/XIN 59 I/O General-purpose digital I/O

Input terminal for crystal oscillator XT1
AVCC 60 S Analog power supply
P2.5/PM_SVMOUT/CB5/A5/ VREF+/VeREF+ 61 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: SVM output

Comparator input CB5

Analog input A5 – ADC

Output of positive reference voltage

Input for an external positive reference voltage to the ADC
P2.4/PM_RTCCLK/CB4/A4/ VREF-/VeREF- 62 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: RTCCLK output

Comparator input CB4

Analog input A4 – ADC

Output of negative reference voltage

Input for an external negative reference voltage to the ADC
P2.2/PM_TA1CCR1A/CB2/A2 63 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: TA1 CCR1 compare output/capture input

Comparator input CB2

Analog input A2 – ADC
P2.1/PM_TA1CCR0A/CB1/A1 64 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: TA1 CCR0 compare output/capture input

Comparator input CB1

Analog input A1 – ADC
Exposed die attach pad Ground supply

The exposed die attach pad must be connected to a solid ground plane as this is the ground connection for the chip.

(1) I = input, O = output, S = supply, G = ground