SLAS834C
November 2012 – December 2014
RF430FRL152H
,
RF430FRL153H
,
RF430FRL154H
PRODUCTION DATA.
1
Device Overview
1.1
Features
1.2
Applications
1.3
Description
1.4
Functional Block Diagram
2
Revision History
3
Device Comparison
4
Terminal Configuration and Functions
4.1
Pin Diagram
4.2
Signal Descriptions
4.3
Pin Multiplexing
4.4
Connections for Unused Pins
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Recommended Operating Conditions, Resonant Circuit
5.5
Active Mode Supply Current Into VDDB Excluding External Current
5.6
Low-Power Mode Supply Current (Into VDDB) Excluding External Current
5.7
Digital I/Os (P1, RST/NMI)
5.8
High-Frequency Oscillator (4 MHz), HFOSC
5.9
Low-Frequency Oscillator (256 kHz), LFOSC
5.10
Wake-Up From Low-Power Modes
5.11
Timer_A
5.12
eUSCI (SPI Master Mode) Recommended Operating Conditions
5.13
eUSCI (SPI Master Mode)
5.14
eUSCI (SPI Slave Mode)
5.15
eUSCI (I2C Mode)
5.16
FRAM
5.17
JTAG
5.18
RFPMM, Power Supply Switch
5.19
RFPMM, Bandgap Reference
5.20
RFPMM, Voltage Doubler
5.21
RFPMM, Voltage Supervision
5.22
SD14, Performance
5.23
SVSS Generator
5.24
Thermistor Bias Generator
5.25
Temperature Sensor
5.26
RF13M, Power Supply and Recommended Operating Conditions
5.27
RF13M, ISO/IEC 15693 ASK Demodulator
5.28
RF13M, ISO/IEC 15693 Compliant Load Modulator
6
Detailed Description
6.1
CPU
6.2
Instruction Set
6.3
Operating Modes
6.4
Interrupt Vector Addresses
6.5
Memory
6.5.1
FRAM
6.5.2
SRAM
6.5.3
Application ROM
6.6
Peripherals
6.6.1
Digital I/O, (P1.x)
6.6.2
Versatile I/O Port P1
6.6.3
Oscillator and System Clock
6.6.4
Compact System Module (C-SYS_A)
6.6.5
Watchdog Timer (WDT_A)
6.6.6
Reset, NMI, SVMOUT System
6.6.7
Timer_A (Timer0_A3)
6.6.8
Enhanced Universal Serial Communication Interface (eUSCI_B0)
6.6.9
ISO/IEC 15693 Analog Front End (RF13M)
6.6.10
ISO/IEC 15693 Decoder/Encoder (RF13M)
6.6.11
CRC16 Module (CRC16)
6.6.12
14-Bit Sigma-Delta ADC (SD14)
6.6.13
Programmable Gain Amplifier (SD14)
6.6.14
Peripheral Register Map
6.7
Port Schematics
6.7.1
Port P1.0 Input/Output
6.7.2
Port P1.1 Input/Output
6.7.3
Port P1.2 Input/Output
6.7.4
Port P1.3 Input/Output
6.7.5
Port P1.4 Input/Output
6.7.6
Port P1.5 Input/Output
6.7.7
Port P1.6 Input/Output
6.7.8
Port P1.7 Input/Output
6.8
Device Descriptors (TLV)
7
Applications, Implementation, and Layout
8
Device and Documentation Support
8.1
Device Support
8.1.1
Development Support
8.1.2
Device and Development Tool Nomenclature
8.2
Documentation Support
8.3
Related Links
8.4
Community Resources
8.5
Trademarks
8.6
Electrostatic Discharge Caution
8.7
Glossary
9
Mechanical Packaging and Orderable Information
9.1
Packaging Information
Package Options
Mechanical Data (Package|Pins)
RGE|24
MPQF124G
Thermal pad, mechanical data (Package|Pins)
RGE|24
QFND024AD
Orderable Information
slas834c_oa
slas834c_pm