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The SMJ320F240 is a member of a family of digital signal processor (DSP) controllers based on the TMS320C2xx generation of 16-bit fixed-point DSPs. This family is optimized for digital motor/motion control applications and contains 16K words of flash memory on chip. The DSP controller combines the enhanced TMS320 architectural design of the C2xLP core CPU for low-cost, high-performance processing capabilities and several advanced peripherals optimized for motor/motion control applications. These peripherals include the event manager module, which provides general-purpose timers and compare registers to generate up to 12 PWM outputs, and a dual 10-bit analog-to-digital converter (ADC), which can perform two simultaneous conversions within 6.1 µs.
The functional block diagram provides a high-level description of each component in the F240 DSP controller. The SMJ320F240 device is composed of three main functional units: a C2xx DSP core, internal memory, and peripherals. In addition to these three functional units, there are several system-level features of the F240 that are distributed. These system features include the memory map, device reset, interrupts, digital input/output (I /O), clock generation, and low-power operation.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | SMJ320F240 DSP Controller datasheet (Rev. C) | 16 Sep 2004 | |
| * | SMD | SMJ320F240 SMD 5962-98612 | 21 Jun 2016 | |
| More literature | SMJ320F240 DSP Controller (Rev. A) | 02 Apr 2001 | ||
| More literature | SM/sMJ320F240 Military DSPs | 21 Jul 1999 |
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| Package | Pins | Download |
|---|---|---|
| CFP (HFP) | 132 | View options |
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