SN54HC74-SP Dual D-type Positive-Edge-Triggered Flip-Flops With Clear And Preset | TI.com

SN54HC74-SP
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Dual D-type Positive-Edge-Triggered Flip-Flops With Clear And Preset

 

Description

The SNx4HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

Features

  • Wide Operating Voltage Range: 2 V to 6 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 40-µA Maximum ICC
  • Typical tpd = 15 ns
  • ±4-mA Output Drive at 5 V
  • Very Low Input Current of 1 µA

Parametrics

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Part number Order Technology Family Input type Output type VCC (Min) (V) VCC (Max) (V) Channels (#) Clock Frequency (Max) (MHz) ICC (uA) IOL (Max) (mA) IOH (Max) (mA) Features Rating Package Group
SN54HC74-SP Order now HC     Standard CMOS     Push-Pull     2     6     2     25     40     5.2     -5.2     Balanced outputs
High speed (tpd 10-50ns)
Positive input clamp diode    
Space     CDIP | 14
CFP | 14