SN54LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS | TI.com

SN54LVC574A
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OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS - SN54LVC574A
Datasheet
 

Description

The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.

These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

Features

  • Operate From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Specified From -40°C to 85°C, -40°C to 125°C, and -55°C to 125°C
  • Max tpd of 7 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Parametrics

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Part number Order Technology Family Input type Output type VCC (Min) (V) VCC (Max) (V) Channels (#) Clock Frequency (Max) (MHz) ICC (uA) IOL (Max) (mA) IOH (Max) (mA) Features Rating Package Group
SN54LVC574A Order now LVC     Standard CMOS     3-State     2     3.6     8     100     10     24     -24     Balanced outputs
Very high speed (tpd 5-10ns)
Over-voltage tolerant inputs
Partial power down (Ioff)    
Military     CDIP | 20
CFP | 20    
SN74LVC574A Order now LVC     Standard CMOS     3-State     1.65     3.6     8     100     10     24     -24     Balanced outputs
Very high speed (tpd 5-10ns)
Over-voltage tolerant inputs
Partial power down (Ioff)    
Catalog     PDIP | 20
SOIC | 20
SO | 20
SSOP | 20
TSSOP | 20
TVSOP | 20
VQFN | 20    
SN74LVC574A-EP Samples not available LVC     Standard CMOS     3-State     2     3.6     8     100     10     24     -24     Balanced outputs
Very high speed (tpd 5-10ns)
Over-voltage tolerant inputs
Partial power down (Ioff)    
HiRel Enhanced Product     TSSOP | 20    
SN74LVC574A-Q1 Samples not available LVC     Standard CMOS     3-State     2     3.6     8     100     10     24     -24     Balanced outputs
Very high speed (tpd 5-10ns)
Over-voltage tolerant inputs
Partial power down (Ioff)    
Automotive     SOIC | 20
TSSOP | 20