SLOS913A October   2015  – February 2017 SN55HVD75-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics: 20 Mbps Device, Bit Time ≥50 ns
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
        5. 9.2.1.5 Transient Protection
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 External Transient Protection
        2. 9.2.2.2 Isolated Bus Node Design
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over recommended operating range (unless otherwise specified) (1)
MIN MAX UNIT
Supply voltage, VCC –0.5 5.5 V
Voltage at A or B inputs –13 16.5 V
Input voltage at any logic pin –0.3 5.7 V
Voltage input, transient pulse, A and B, through 100 Ω –100 100 V
Receiver output current –24 24 mA
Junction temperature, TJ 170 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) All pins ±8000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) All pins ±1500
JEDEC standard 22, test method A115 (machine model) All pins ±300
IEC 61000-4-2 ESD (air-gap discharge)(3) Pins 5 to 7 ±12000
IEC 61000-4-2 ESD (contact discharge) Pins 5 to 7 ±12000
IEC 61000-4-4 EFT (fast transient or burst) Pins 5 to 7 ±4000
IEC 60749-26 ESD HBM Pins 5 to 7 ±15000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) By inference from contact discharge results, see Application and Implementation.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
VI Input voltage at any bus terminal (separately or common mode)(1) –7 12 V
VIH High-level input voltage (driver, driver enable, and receiver enable inputs) 2 VCC V
VIL Low-level input voltage (driver, driver enable, and receiver enable inputs) 0 0.8 V
VID Differential input voltage –12 12 V
IO Output current, driver –60 60 mA
IO Output current, receiver –8 8 mA
RL Differential load resistance 54 60 Ω
CL Differential load capacitance 50 pF
1/tUI Signaling rate 20 Mbps
TA(2) Operating free-air temperature (see Thermal Information) –55 125 °C
TJ Junction temperature –55 150 °C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet.
(2) Operation is specified for internal (junction) temperatures up to 150°C. Self-heating due to internal power dissipation should be considered for each application. Maximum junction temperature is internally limited by the thermal shutdown (TSD) circuit which disables the driver outputs when the junction temperature reaches 170°C.

6.4 Thermal Information

THERMAL METRIC(1) SN55HVD75-EP UNIT
DRB (VSON)
8 PINS
RθJA Junction-to-ambient thermal resistance 40.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 49.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.9 °C/W
RθJB Junction-to-board thermal resistance 15.5 °C/W
ψJT Junction-to-top characterization parameter 0.6 °C/W
ψJB Junction-to-board characterization parameter 15.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended operating range (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOD| Driver differential output voltage magnitude RL = 60 Ω, 375 Ω on each output to
–7 V to 12 V		 See Figure 6 1.5 2 V
RL = 54 Ω (RS-485) See Figure 7 1.5 2
RL = 100 Ω 1.8 2.5
Δ|VOD| Change in magnitude of driver differential output voltage RL = 54 Ω, CL = 50 pF –50 0 50 mV
VOC(SS) Steady-state common-mode output voltage Center of two 27-Ω load resistors 1 VCC/2 3 V
ΔVOC Change in differential driver output common-mode voltage –50 0 50 mV
VOC(PP) Peak-to-peak driver common-mode output voltage 200 mV
COD Differential output capacitance 15 pF
VIT+ Positive-going receiver differential input voltage threshold See (1) –70 –20 mV
VIT– Negative-going receiver differential input voltage threshold –200 –150 See (1) mV
VHYS Receiver differential input voltage threshold hysteresis (VIT+ – VIT–) 50 80 mV
VOH Receiver high-level output voltage IOH = –8 mA 2.4 VCC – 0.3 V
VOL Receiver low-level output voltage IOL = 8 mA 0.2 0.4 V
II Driver input, driver enable, and receiver enable input current –2.75 2.75 µA
IOZ Receiver output high-impedance current VO = 0 V or VCC, RE at VCC –1 1 µA
IOS Driver short-circuit output current –165 165 mA
II Bus input current (disabled driver) VCC = 3 V to 3.6 V or
VCC = 0 V
DE at 0 V		 VI = 12 V 75 150 µA
VI = –7 V –100 –40
ICC Supply current (quiescent) Driver and receiver enabled DE = VCC, RE = GND
No load 		750 950 µA
Driver enabled, receiver disabled DE = VCC, RE = VCC
No load 		300 500
Driver disabled, receiver enabled DE = GND, RE = GND
No load		 600 800
Driver and receiver disabled DE = GND, D = open
RE = VCC, No load 		0.1 2
Supply current (dynamic) See Typical Characteristics
(1) Under any specific conditions, VIT+ is assured to be at least VHYS higher than VIT–.

6.6 Switching Characteristics: 20 Mbps Device, Bit Time ≥50 ns

over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRIVER
tr, tf Driver differential output rise or fall time RL = 54 Ω
CL = 50 pF		 See Figure 8 1 7 14 ns
tPHL, tPLH Driver propagation delay 6 11 17 ns
tSK(P) Driver pulse skew, |tPHL – tPLH| 0 2 ns
tPHZ, tPLZ Driver disable time See Figure 9 and Figure 10 12 50 ns
tPZH, tPZL Driver enable time Receiver enabled 10 20 ns
Receiver disabled 3 7 µs
RECEIVER
tr, tf Receiver output rise or fall time CL = 15 pF See Figure 11 5 10 ns
tPHL, tPLH Receiver propagation delay time 60 70 ns
tSK(P) Receiver pulse skew, |tPHL – tPLH| 0 6 ns
tPLZ, tPHZ Receiver disable time 15 30 ns
tpZL(1), tPZH(1), tPZL(2), tPZH(2) Receiver enable time Driver enabled See Figure 12 10 50 ns
Driver disabled See Figure 13 3 8 µs

6.7 Typical Characteristics

SN55HVD75-EP drvo_io_slos913.gif
VCC = 3.3 V DE = VCC D = 0 V
Figure 1. Driver Output Voltage vs Driver Output Current
SN55HVD75-EP io_vcc_4_slos913.gif
TA = 25°C RL = 54 Ω D = VCC
DE = VCC
Figure 3. Driver Output Current vs Supply Voltage
SN55HVD75-EP rec_outin_llsE11.gif
Figure 5. Receiver Output vs Input
SN55HVD75-EP difvo_io_slos913.gif
VCC = 3.3 V DE = VCC D = 0 V
Figure 2. Driver Differential Output Voltage vs Driver Output Current
SN55HVD75-EP sup_cur_HVD75_slos913.gif
RL = 54 Ω
Figure 4. Supply Current vs Signal Rate