SLLSE49D September   2010  – July 2017 SN65HVD1780-Q1 , SN65HVD1781-Q1 , SN65HVD1782-Q1

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings—AEC
    3. 6.3  ESD Ratings—IEC
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Power Dissipation Ratings
    8. 6.8  Switching Characteristics
    9. 6.9  Package Dissipation Ratings
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bus Fault Conditions
      2. 8.3.2 Receiver Failsafe
      3. 8.3.3 Hot-Plugging
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Bus Loading
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Stub Length
        2. 9.2.2.2 Receiver Failsafe
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The SN65HVD1780-Q1, SN65HVD1781-Q1, and SN65HVD1782-Q1 devices are half-duplex RS-485 transceivers available in three speed grades suitable for data transmission up to 115 kbps, 1 Mbps, and 10 Mbps.

These devices feature a wide common-mode operating range and bus-pin fault protection up to ±70 V. Each device has an active-high driver enable and active-low receiver enable. A standby current of less than 1 µA can be achieved by disabling both driver and receiver.

8.2 Functional Block Diagram

SN65HVD1780-Q1 SN65HVD1781-Q1 SN65HVD1782-Q1 FBD_SLLSE49.gif

8.3 Feature Description

Internal ESD protection circuits protect the transceiver bus terminals against ±16-kV Human Body Model (HBM) electrostatic discharges.

Device operation is specified over a wide temperature range from –40°C to 125°C.

8.3.1 Bus Fault Conditions

The SN65HVD178x-Q1 family of RS-485 transceivers is designed to survive bus pin faults up to ±70 V. The SN65HVD1782-Q1 device will not survive a bus pin fault with a direct short to voltages above 30 V when all of the following occurs:

  • The device is powered on
  • The driver is enabled (DE = HIGH), and one of of the following is true
    • D = HIGH AND the bus fault is applied to the A pin
    • D = LOW AND the bus fault is applied to the B pin

Under other conditions, the device survives shorts to bus pin faults up to ±70 V. Table 1 summarizes the conditions under which the device may be damaged, and the conditions under which the device will not be damaged.

Table 1. Bus Fault Conditions for the HVD1782

POWER DE D A B RESULTS
OFF X X –70 V < VA < 70 V –70 V < VB < 70 V Device survives
ON LO X –70 V < VA < 70 V –70 V < VB < 70 V Device survives
ON HI L –70 V < VA < 70 V –70 V < VB < 30 V Device survives
ON HI L –70 V < VA < 70 V 30 V < VB Damage may occur
ON HI H –70 V < VA < 30 V –70 V < VB < 30 V Device survives
ON HI H 30 V < VA –70 V < VB < 30 V Damage may occur

8.3.2 Receiver Failsafe

The SN65HVD178x-Q1 family of half-duplex transceivers provides internal biasing of the receiver input thresholds in combination with large input-threshold hysteresis. At a positive input threshold of VIT+ = –35 mV and an input hysteresis of VHYS = 30 mV, the receiver output remains logic high under bus-idle, bus-short, or open bus conditions in the presence of up to 130-mVPP differential noise without the need for external failsafe biasing resistors.

8.3.3 Hot-Plugging

These devices are designed to operate in hot swap or hot-pluggable applications. Key features for hot-pluggable applications are power-up and power-down glitch free operation, default disabled input and output pins, and receiver failsafe.

As shown in the Functional Block Diagram, an internal power-on reset circuit keeps the driver outputs in a high impedance state until the supply voltage has reached a level at which the device will reliably operate. This circuit ensures that no problems occur on the bus pin outputs as the power supply turns on or off.

As shown in Device Functional Modes, the driver and receiver enable inputs (DE and RE) are disabled by default. This default ensures that the device neither drives the bus nor reports data on the R pin until the associated controller actively drivers the enable pins.

8.4 Device Functional Modes

When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is negative.

When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output A turns high and B turns low.

Table 2. Driver Function Table

INPUT ENABLE OUTPUTS DRIVER STATE
D DE A B
H H H L Actively drive bus High
L H L H Actively drive bus Low
X L Z Z Driver disabled
X OPEN Z Z Driver disabled by default
OPEN H H L Actively drive bus High by default

When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R, turns high. When VID is negative and lower than the negative input threshold, VIT–, the receiver output, R, turns low. If VID is between VIT+ and VIT– the output is indeterminate.

When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus).

Table 3. Receiver Function Table

DIFFERENTIAL INPUT ENABLE OUTPUT RECEIVER STATE
VID = VA – VB RE R
VID > VIT+ L H Receive valid bus High
VIT– < VID < VIT+ L ? Indeterminate bus state
VID < VIT– L L Receive valid bus Low
X H Z Receiver disabled
X OPEN Z Receiver disabled by default
Open-circuit bus L H Fail-safe high output
Short-circuit bus L H Fail-safe high output
Idle (terminated) bus L H Fail-safe high output