SLLSE49D September   2010  – July 2017 SN65HVD1780-Q1 , SN65HVD1781-Q1 , SN65HVD1782-Q1

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings—AEC
    3. 6.3  ESD Ratings—IEC
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Power Dissipation Ratings
    8. 6.8  Switching Characteristics
    9. 6.9  Package Dissipation Ratings
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bus Fault Conditions
      2. 8.3.2 Receiver Failsafe
      3. 8.3.3 Hot-Plugging
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Bus Loading
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Stub Length
        2. 9.2.2.2 Receiver Failsafe
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from C Revision (April 2016) to D Revision

  • Changed the differential input to receive a valid bus high from VID < VIT+ to VID > VIT+ in the Receiver Function TableGo
  • Changed the Half-Duplex Layout ExampleGo
  • Added the Receiving Notification of Documentation Updates sectionGo
  • Changed the Electrostatic Discharge Caution statementGo

Changes from B Revision (January 2016) to C Revision

  • Changed the signaling rate for SN65HVD1780-Q1 from 115 to 0.115 Bin the Recommended Operating Conditions table Go

Changes from A Revision (August 2015) to B Revision

  • Changed HBM and CDM back to the AEC specification and split the IEC specification into a separate table Go
  • Added the SN65HVD1780-Q1 and SN65HVD1782-Q1 devices to the Thermal Information tableGo

Changes from * Revision (September 2010) to A Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Added new ListItem in Features, second one with sub list itemsGo