Product details

Technology family ABT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 10 IOL (max) (mA) 12 Supply current (max) (µA) 40000 IOH (max) (mA) -12 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Damping resistors, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family ABT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 10 IOL (max) (mA) 12 Supply current (max) (µA) 40000 IOH (max) (mA) -12 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Damping resistors, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • Output Ports Have Equivalent 25- Series Resistors, So No External Resistors Are Required
  • State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • Package Options Include Plastic Small-Outline (DW) Package, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs

    EPIC-IIB is a trademark of Texas Instruments Incorporated.

     

  • Output Ports Have Equivalent 25- Series Resistors, So No External Resistors Are Required
  • State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • Package Options Include Plastic Small-Outline (DW) Package, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs

    EPIC-IIB is a trademark of Texas Instruments Incorporated.

     

These 10-bit buffers or bus drivers provide a high-performance bus interface for wide data paths or buses carrying parity.

The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable ( or ) input is high, all ten outputs are in the high-impedance state. The 'ABT2827 provide true data at their outputs.

To ensure the high-impedance state during power up or power down, should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

The SN54ABT2827 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT2827 is characterized for operation from -40°C to 85°C.

 

 

These 10-bit buffers or bus drivers provide a high-performance bus interface for wide data paths or buses carrying parity.

The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable ( or ) input is high, all ten outputs are in the high-impedance state. The 'ABT2827 provide true data at their outputs.

To ensure the high-impedance state during power up or power down, should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

The SN54ABT2827 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT2827 is characterized for operation from -40°C to 85°C.

 

 

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Technical documentation

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Type Title Date
* Data sheet 10-Bit Buffers/Drivers With 3-State Outputs datasheet (Rev. A) 01 Jan 1997
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note Quad Flatpack No-Lead Logic Packages (Rev. D) 16 Feb 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
Selection guide Advanced Bus Interface Logic Selection Guide 09 Jan 2001
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) 01 Mar 1997
Application note Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74ABT2827 Behavioral SPICE Model

SCBM140.ZIP (7 KB) - PSpice Model
Package Pins Download
SOIC (DW) 24 View options

Ordering & quality

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Information included:
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Support & training

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